10

AT25F512/1024

1440P–SEEPR–6/04

The READY/BUSY status of the device can be determined by initiating a RDSR instruc-

tion. If Bit 0 = 1, the program cycle is still in progress. If Bit 0 = 0, the program cycle has

ended. Only the RDSR instruction is enabled during the program cycle.

A single PROGRAM instruction programs 1 to 256 consecutive bytes within a page if it

is not write protected. The starting byte could be anywhere within the page. When the

end of the page is reached, the address will wrap around to the beginning of the same

page. If the data to be programmed are less than a full page, the data of all other bytes

on the same page will remain unchanged. If more than 256 bytes of data are provided,

the address counter will roll over on the same page and the previous data provided will

be replaced. The same byte cannot be reprogrammed without erasing the whole sector

first. The AT25F512/1024 will automatically return to the write disable state at the com-

pletion of the PROGRAM cycle.

Note:

If the device is not write enabled (WREN), the device will ignore the Write instruction and

will return to the standby state, when CS is brought high. A new CS falling edge is

required to re-initiate the serial communication.

Note:

1. For the AT25F512, A16 must be set to zero. If A16 of the AT25F512 is set to ONE,

READ data out are undetermined and PROGRAM, SECTOR ERASE and CHIP

ERASE may incur busy cycles.

SECTOR ERASE (SECTOR ERASE): Before a byte can be reprogrammed, the sector

which contains the byte must be erased. In order to erase the AT25F512/1024, two sep-

arate instructions must be executed. First, the device must be write enabled via the

WREN instruction. Then the SECTOR ERASE instruction can be executed.

The SECTOR ERASE instruction erases every byte in the selected sector if the sector is

not locked out. Sector address is automatically determined if any address within the sec-

tor is selected. The SECTOR ERASE instruction is internally controlled; it will

automatically be timed to completion. During this time, all commands will be ignored,

except RDSR instruction. The AT25F512/1024 will automatically return to the write dis-

able state at the completion of the SECTOR ERASE cycle.

CHIP ERASE (CHIP ERASE): As an alternative to the SECTOR ERASE, the CHIP

ERASE instruction will erase every byte in all sectors that are not locked out. First, the

device must be write enabled via the WREN instruction. Then the CHIP ERASE instruc-

tion can be executed. The CHIP ERASE instruction is internally controlled; it will

automatically be timed to completion. The CHIP ERASE cycle time typically is 3.5 sec-

onds. During the internal erase cycle, all instructions will be ignored except RDSR. The

AT25F512/1024 will automatically return to the write disable state at the completion of

the CHIP ERASE cycle.

Table 6. Address Key

Address

AT25F512

AT25F1024

Zeros

A

16

(1)

-

Don’t Care Bits

Table 7. Sector Addresses

Sector Address

AT25F512 Sector

AT25F1024 Sector

000000 to 007FFF

Sector 1

Sector 1

008000 to 00FFFF

Sector 2

Sector 2

010000 to 017FFF

N/A

Sector 3

018000 to 01FFFF

N/A

Sector 4