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FXMHD103 Datasheet(PDF) 3 Page - Fairchild Semiconductor |
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FXMHD103 Datasheet(HTML) 3 Page - Fairchild Semiconductor |
3 / 16 page © 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FXMHD103 • Rev. 1.0.2 3 Block Diagrams (Continued) Figure 3. Circuit Block Diagram Table 1. Truth Table (VCCA & VCCC Valid) OE HPD_C OE Internal VREG HPD_H SCL_C SDA_C CEC_C LOW Don’t Care LOW Disabled 3-State 3-State 3-State 3-State HIGH LOW LOW Disabled Enabled 3-State (2) 3-State (2) 3-State (2) HIGH HIGH HIGH Enabled Enabled Enabled Enabled Enabled Note: 2. SCL_C and SDA_C internally pulled up to VCCC. CEC_C is 0V because VREG is disabled. This is required for HDMI compliance testing. The VOUTDIS parameter captures this requirement. |
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