6

5087E–SEEPR–7/09

AT25010A/020A/040A/080A

5.

Functional Description

The AT25010A/020A/040A is designed to interface directly with the synchronous serial periph-

eral interface (SPI) of the 6805 and 68HC11 series of microcontrollers.

The AT25010A/020A/040A utilizes an 8-bit instruction register. The list of instructions and their

operation codes are contained in Table 5-1. All instructions, addresses, and data are transferred

with the MSB first and start with a high-to-low CS transition.

Note:

“A” represents MSB address bit A8.

WRITE ENABLE (WREN): The device will power up in the write disable state when V

applied. All programming instructions must therefore be preceded by a Write Enable instruction.

The WP pin must be held high during a WREN instruction.

WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable

instruction disables all programming modes. The WRDI instruction is independent of the status

of the WP pin.

READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to

the status register. The READY/BUSY and Write Enable status of the device can be determined

by the RDSR instruction. Similarly, the block write protection bits indicate the extent of protection

employed. These bits are set by using the WRSR instruction.

Table 5-1.

Instruction Set for the AT25010A/020A/040A

Instruction Name

Instruction Format

Operation

WREN

0000 X110

Set Write Enable Latch

WRDI

0000 X100

Reset Write Enable Latch

RDSR

0000 X101

Read Status Register

WRSR

0000 X001

Write Status Register

READ

0000 A011

Read Data from Memory Array

WRITE

0000 A010

Write Data to Memory Array

Table 5-2.

Status Register Format

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

X

X

X

X

BP1

BP0

WEN

RDY