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ATTINY13 Datasheet(PDF) 7 Page - ATMEL Corporation |
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ATTINY13 Datasheet(HTML) 7 Page - ATMEL Corporation |
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7 / 176 page  7 2535J–AVR–08/10 ATtiny13 4. CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 4.1 Architectural Overview Figure 4-1. Block Diagram of the AVR Architecture In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being executed, the next instruc- tion is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash memory. Flash Program Memory Instruction Register Instruction Decoder Program Counter Control Lines 32 x 8 General Purpose Registrers ALU Status and Control I/O Lines EEPROM Data Bus 8-bit Data SRAM Interrupt Unit Watchdog Timer Analog Comparator I/O Module 2 I/O Module1 I/O Module n |
Similar Part No. - ATTINY13_14 |
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Similar Description - ATTINY13_14 |
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