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GA15IDDJT22-FR4 Datasheet(PDF) 1 Page - GeneSiC Semiconductor, Inc.

Part # GA15IDDJT22-FR4
Description  Gate Driver for SiC SJT with Output and Signal Isolation
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Manufacturer  GENESIC [GeneSiC Semiconductor, Inc.]
Direct Link  http://www.genesicsemi.com/
Logo GENESIC - GeneSiC Semiconductor, Inc.

GA15IDDJT22-FR4 Datasheet(HTML) 1 Page - GeneSiC Semiconductor, Inc.

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Isolated Gate Driver
GA15IDDJT22-FR4
Sep 2014
Pg1 of 5
Gate Driver for SiC SJT with Output
and Signal Isolation
Features
Package
 Requires single 12 V voltage supply
 Two-voltage level topology with low drive losses
 High-side drive capable with 2200 V min. supply isolation
 6000 V Signal Isolation (up to 10 s)
 Capable of high Gate Currents with 3 W Maximum Power
 RoHS Compliant
 
Suitable for driving
 GA50JT12-247
 GA50JT12-247
 GA50SICP12-227
 GA100SICP12-227
Gate Drive Theory of Operation
The SJT transistor is a current controlled transistor which requires a positive gate current for turn-on as well as to remain in on-state. An ideal
gate current waveform for ultra-fast switching of the SJT, while maintaining low gate drive losses, is shown in Figure 1.
Figure 1: Idealized Gate Current Waveform
Gate Currents, IG,pk/-IG,pk and Voltages during Turn-On and Turn-Off
An SJT is rapidly switched from its blocking state to on-state, when the necessary gate charge, QG, for turn-on is supplied by a burst of high
gate current, IG,on, until the gate-source capacitance, CGS, and gate-drain capacitance, CGD, are fully charged.
,
As an example, an IG,pon ≥ 3 A is required to achieve a 25 ns VDS fall time for a 800 V switching transition, due to the gate-drain charge, QGD of
77 nC for the GA20JT12-247. The IG,pon pulse should ideally terminate, when the drain voltage falls to its on-state value, in order to avoid
unnecessary drive losses during the steady on-state. In practice, the rise time of the IG,on pulse is affected by the parasitic inductances, Lpar in
the TO-247 package and drive circuit. A voltage developed across the parasitic inductance in the source path, Ls, can de-bias the gate-source
junction, when high drain currents begin to flow through the device. The applied gate voltage should be maintained high enough, above the
VGS,ON level to counter these effects.
A high negative peak current, -IG,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from
the gate, and achieve rapid turn-off. While satisfactory turn off can be achieved with VGS = 0 V, a negative gate voltage VGS may be used in
order to speed up the turn-off transition.
VISO,min
=
2200 V
PDrive, cont
=
15 W
PDrive,switch
=
> 3 W
fMAX
=
TBD


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