6

3672A–CNFG–1/08

AT18F010/002/040/080 [Preliminary]

6.

Pin Description

6.1

DATA (D0)

Open-collector bi-directional data pin. This pin has an internal 20 K

Ω pull-up resistor.

6.2

CLK

Clock input. Used to increment the internal address and bit counter for reading and program-

ming. This pin has an internal 20 K

Ω pull-up resistor.

6.3

RESET/OE

Output Enable (active High) and RESET (active Low). A Low level on RESET/OE resets both

the address and bit counters. A High level (with CE Low) enables the data output driver. This pin

has an internal 20 K

Ω pull-up resistor.

6.4

CE

Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the address

counter and enables the data output driver. A High level on CE disables both the address and bit

counters and forces the device into a low-power standby mode. This pin has an internal 20 K

Ω

pull-up resistor.

6.5

CF

Configuration Pulse (open-drain output). Allows JTAG CONFIG instruction to initiate FPGA con-

figuration without powering down the FPGA. This is an open-drain output that is pulsed Low by

the JTAG CONFIG command.

Table 6-1.

Pin Descriptions

Name

Type

20-lead TSSOP

DATA

I/O

1

CLK

I

3

RESET/OE

I

8

CE

I10

CF

I7

CEO

O13

TMS

I

5

TCK

I

6

TDI

I

4

TDO

O

17

VCCINT

I

18

NC

-

2, 9, 12, 14, 15, 16

VCCO

Power Supply

19

GND

Ground

11

VCCJ

Power Supply

20