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3714AS–MICRO–7/11

AT89LP51RD2/ED2/ID2 Summary - Preliminary

2.3

Comparison to the Atmel AT89C51RD2/ED2/ID2

The Atmel

are fully binary compatible with the 8051 instruction set. The AT89LP51RD2/ED2/ID2 has two

modes of operations, Compatibility mode and Fast mode. In Compatibility mode the instruction

timing, peripheral behavior, SFR addresses, bit assignments and pin functions are identical to

the existing Atmel AT89C51RD2/ED2/ID2 product. Additional enhancements are transparent to

the user and can be used if desired. Fast mode allows greater performance, but with some dif-

ferences in behavior. The major enhancements from the AT89C51RD2/ED2/ID2 are outlined in

the following paragraphs and may be useful to users migrating to the AT89LP51RD2/ED2/ID2

from older devices. A summary of the differences between Compatibility and Fast modes is

give n in T ab le 2- 3 on p a ge 1 1 . Se e a l s o th e App l ic a tio n no te “M igr a ting fr om

AT89C51RD2/ED2/ID2 to AT89LP51RD2/ED2/ID2.”

2.3.1

Instruction Execution

cycle of the standard 8051 where instruction bytes are fetched every three system clock cycles.

Execution times in this mode are identical to the Atmel AT89C51RD2/ED2/ID2. For greater per-

formance the user can enable Fast mode by disabling the Compatibility fuse. In Fast mode the

CPU fetches one code byte from memory every clock cycle instead of every three clock cycles.

This greatly increases the throughput of the CPU. Each standard instruction executes in only

one to four clock cycles. See datasheet for more details. Any software delay loops or instruction-

based timing operations may need to be retuned to achieve the desired results in Fast mode.

2.3.2

System Clock

The system clock source is not limited to a crystal or external clock. The system clock source is

selectable between the crystal oscillator, an externally driven clock and an internal 8.0MHz RC

oscillator for AT89LP51RD2/ED2 and clock source A of AT89LP51ID2. Clock source B of

AT89LP51ID2 is not limited to a 32 kHz crystal. The clock source B is selectable between the 32

kHz crystal oscillator, an externally driven clock and an internal 8.0MHz RC oscillator. Unlike

AT89C51ID2, the X2 and CKRL features will also affect the OSCB source.

By default in Compatibility mode the system clock frequency is divided by 2 from the externally

supplied XTAL1 frequency for compatibility with standard 8051s (12 clocks per machine cycle).

The System Clock Divider can scale the system clock versus the oscillator source. The divide-

by-2 can be disabled to operate in X2 mode (6 clocks per machine cycle) or the clock may be

further divided to reduce the operating frequency. In Fast mode the clock divider defaults to

divide by 1.

2.3.3

Reset

The RST pin of the AT89LP51RD2/ED2/ID2 has selectable polarity using the POL pin (formerly

EA). When POL is high the RST pin is active high with a pull-down resistor and when POL is low

the RST pin is active low with a pull-up resistor. For existing AT89C51RD2/ED2/ID2 sockets

where EA is tied to VDD, replacing AT89C51RD2/ED2 with AT89LP51RD2/ED2/ID2 will main-

tain the active high reset. Note that forcing external execution by tying EA low is not supported.

The AT89LP51RD2/ED2/ID2 includes an on-chip Power-On Reset and Brown-out Detector cir-

cuit that ensures that the device is reset from system power up. In most cases a RC startup

circuit is not required on the RST pin, reducing system cost, and the RST pin may be left uncon-

nected if a board-level reset is not present.