7

5087E–SEEPR–7/09

AT25010A/020A/040A/080A

WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of

four levels of protection. The AT25010A/020A/040A is divided into four array segments. One-

quarter, one-half, or all of the memory segments can be protected. Any of the data within any

selected segment will therefore be read only. The block write protection levels and correspond-

ing status register control bits are shown in Table 5-4.

Bits BP0 and BP1 are nonvolatile cells that have the same properties and functions as the regu-

lar memory cells (e.g., WREN, t

READ SEQUENCE (READ): Reading the AT25010A/020A/040A via the serial output (SO) pin

requires the following sequence. After the CS line is pulled low to select a device, the read op-

code (including A8) is transmitted via the SI line followed by the byte address to be read (A7–

A0). Upon completion, any data on the SI line will be ignored. The data (D7

D0) at the specified

address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be

driven high after the data comes out. The read sequence can be continued since the byte

address is automatically incremented and data will continue to be shifted out. When the highest

address is reached, the address counter will roll over to the lowest address, allowing the entire

memory to be read in one continuous read cycle.

WRITE SEQUENCE (WRITE): In order to program the AT25010A/020A/040A, the Write Protect

(WP) pin must be held high and two separate instructions must be executed. First, the device

must be write enabled via the WREN instruction. Then a write (WRITE) instruction may be exe-

cuted. Also, the address of the memory location(s) to be programmed must be outside the

protected address field location selected by the block write protection level. During an internal

write cycle, all commands will be ignored except the RDSR instruction.

Table 5-3.

Read Status Register Bit Definition

Bit

Definition

Bit0(RDY)

Bit 0 = “0” (RDY) indicates the device is ready. Bit 0 = “1” indicates the write

cycle is in progress.

Bit 1 (WEN)

Bit 1= “0” indicates the device is not write-enabled. Bit 1 = “1” indicates the

device is write-enabled.

Bit 2 (BP0)

See Table 5-4 on page 7.

Bit 3 (BP1)

See Table 5-4 on page 7.

Bits 4

6 are “0”s when device is not in an internal write cycle.

Bits 0

 7 are “1”s during an internal write cycle.

Table 5-4.

Block Write Protect Bits

Level

Status Register Bits

Array Addresses Protected

BP1

BP0

AT25010A

AT25020A

AT25040A

0

0

0

None

None

None

1 (1/4)

0

1

60-7F

C0-FF

180-1FF

2 (1/2)

1

0

40-7F

80-FF

100-1FF

3 (All)

1

1

00-7F

00-FF

000-1FF