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UR5596-S08-R Datasheet(PDF) 5 Page - E-Tech Electronics LTD |
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UR5596-S08-R Datasheet(HTML) 5 Page - E-Tech Electronics LTD |
5 / 12 page UR5596 CMOS IC UNISONICTECHNOLOGIESCO.,LTD 5 of 12 www.unisonic.com.tw QW-R502-045,C PIN DESCRIPTIONS AVIN , PVIN Input supply pins . AVIN is used to supply all the internal analog circuits and PVIN is used to provide the output stage to create VTT. These pins have the capability to work off separate supplies depending on the application. Higher voltages on PVIN will increase the maximum continuous output current because of output RDSON limitations at voltages close to VTT. But the internal power loss will also increase, thermally limiting the design. If the junction temperature exceeds the thermal shutdown than the part will enter a shutdown state identical to the manual shutdown where VTT is tri-stated and VREF remains active. For SSTL-2 applications, a good compromise would be to connect the AVIN and PVIN directly together at 2.5V. This eliminates the need for bypassing the two supply pins separately. The only limitation on input voltage selection is that PVIN must be equal to or lower than AVIN. It is recommended to connect PVIN to voltage rails equal to or less than 3.3V to prevent the thermal limit from tripping because of excessive internal power dissipation. VDDQ The input pin used to create the internal reference voltage from a resistor divider of two internal 50kΩ resistors for regulating VTT and to guarantee VTT will track VDDQ/2 precisely. As a remote sense by connecting VDDQ directly to the 2.5V rail for SSTL-2 applications is an optimal implementation of VDDQ at the DIMM. This ensures that the reference voltage tracks the DDR memory rails precisely without a large voltage drop from the power lines. VSENSE The sense pin supply improved remote load regulation, if remote load regulation is not used then the VSENSE pin must still be connected to VTT. A long trace will cause a significant IR drop resulting in a termination voltage lower at one end of the bus than the other. Connect VSENSE pin to the middle of the bus to provide a better distribution across the entire termination bus then DDR performance will be improved. Take notice of when a long VSENSE trace is implemented in close proximity to the memory, noise pickup in the VSENSE trace can cause problems with precise regulation of VTT. A ceramic capacitor of 0.1uF is placed to next the VSENSE pin can help filter any high frequency signals and preventing errors. VREF VREF supply the buffered output of the internal reference voltage VDDQ/2. This output delivers the reference voltage for the Northbridge chipset and memory. Since these inputs are typically extremely high impedance, there should be little current drawn from VREF. A 0.1µF~0.01µF ceramic capacitor could be used to acquire better performance, located close to the pin to help with noise. This output remains active during the shutdown state and thermal shutdown events for the suspend to RAM functionality. VTT VTT is a regulated output for the bus resistors termination of DDR-SDRAM. It can track precisely the VDDQ/2 voltage with the sinking and sourcing current capability. The UTC UR5596 is designed to handle peak transient currents of up to ± 3A with a fast transient response. If a transient is expected to remain above the maximum continuous current rating for a significant amount of time then the output capacitor size should be large enough to prevent an excessive voltage drop. Although UTC UR5596 can handle large transient output currents, but it can not handling these for long durations since the limited thermal dissipation capability of SOP-8 package. If large currents are required for longer durations, then must ensure the maximum junction temperature is not exceeded, otherwise, the maximum output current will be degraded with heating. Proper thermal de-rating should always be used. While the temperature beyond the junction temperature, the thermal shutdown protection will be functioned, then VTT will tri-state until the part returns below the hysteretic trigger point. |
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