9

80C32E

4149N–AERO–04/07

DC Parameters

Notes:

1. I

V

V

2. Idle I

0.5V; XTAL2 N.C; Port 0 = V

3. Power-down I

ure 5).

4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V

and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0

transitions during bus operation. In the worst cases (capacitive loading 100 pF), the noise pulse on the ALE line may exceed

Maximum I

Maximum I

Port 0: 26 mA

Ports 1, 2 and 3: 15 mA

Maximum total I

Symbol

Parameter

Min.

Max

Unit

Test Conditions

V

IL

Input Low Voltage

-0.5

0.2 V

V

V

IH

Input High Voltage except XTAL1, RST

0.2 V

V

V

V

IH1

Input High Voltage, XTAL1, RST

0.7 V

CC

V

V

V

OL

0.45

V

I

(4)

0.45

V

(4)

V

OH

Output High Voltage, ports 1, 2, 3

2.4

0.75 V

CC

0.9 V

CC

V

V

V

I

I

I

Output High Voltage, port 0, ALE, PSEN

2.4

0.9 V

CC

V

V

V

I

R

RST

RST Pull-down Resistor

50

200

kΩ

Logical 0 Input Current ports 1, 2 and 3

-75

µ

A

Vin = 0.45V

I

LI

Input Leakage Current

±

10

µ

A

0.45 V < Vin < V

CC

I

TL

Logical 1 to 0 Transition Current, ports 1, 2, 3

-750

µ

A

Vin = 2.0V

C

IO

Capacitance of I/O Buffer

10

pF

Fc = 1 MHz

I

PD

75

µ

A

2.0V < V

I

CC

Freq = 1 MHz Icc Op

Freq = 1 MHz Icc Idle

Freq = 6 MHz Icc Op

Freq = 6 MHz Icc Idle

Freq >12 MHz Icc Op

Freq >12 MHz Icc Idle

1.8

1

10

4

1.25F + 5

0.36F + 2.7

mA

mA

mA

mA

mA

mA

V

F in MHz