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HDM8513A Datasheet(PDF) 11 Page - Hynix Semiconductor |
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HDM8513A Datasheet(HTML) 11 Page - Hynix Semiconductor |
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11 / 67 page  11 Table 6: Intel 80C88A Write Cycle Timing Parameters (Busmode = 1) Symbol Parameter Min. Max. Unit tsu1 Input Data Setup before /WE Inactive 20 - ns th1 Input Address, Data and /CE Hold after /WE Inactive 8 - ns tpw1 /WE Low Duration 200 - ns td1 Delay from /CE to DTACK Active - 35 ns tdoz1 Delay from /WE Inactive to DTACK in Tristate Mode - 15 ns Valid HI_ADDR [4:0] /CE /WE DTACK HI_DATA[7:0] th1 tdoz1 tsu1 tpw1 td1 FIGURE 4: INTEL 80C88A WRITE TIMING DIAGRAM Note: HI_ADDR[4:0] is derived from the processor(80C88A) A15-A8 bus and HI_DATA[7:0] is connected to the AD7 - AD0 bus. #This page is only for HDM8513AP. |
Similar Part No. - HDM8513A |
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Similar Description - HDM8513A |
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