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ATAR090-C Datasheet(PDF) 9 Page - ATMEL Corporation |
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ATAR090-C Datasheet(HTML) 9 Page - ATMEL Corporation |
9 / 80 page 9 4700C–4BMCU–02/05 ATAR090-C/ATAR890-C 3.2.7.2 Interrupt Latency The interrupt latency is the time from the occurrence of the interrupt to the interrupt service rou- tine being activated. In MARC4 this is extremely short (taking between 3 to 5 machine cycles depending on the state of the core). Figure 3-6. Interrupt Handling 7 6 5 4 3 2 1 0 INT5 active INT7 active INT2 pending SWI0 INT2 active INT0 pending INT0 active INT2 RTI RTI INT5 INT3 active INT3 RTI RTI RTI INT7 Time Main / Autosleep Main / Autosleep Table 3-1. Interrupt Priority Table Interrupt Priority ROM Address Interrupt Opcode Function INT0 Lowest 040h C8h (SCALL 040h) Software interrupt (SWI0) INT1 | 080h D0h (SCALL 080h) External hardware interrupt, any edge at BP52 or BP53 INT2 | 0C0h D8h (SCALL 0C0h) Timer 1 interrupt INT3 | 100h E8h (SCALL 100h) SSI interrupt or external hardware interrupt at BP40 or BP43 INT4 | 140h E8h (SCALL 140h) Timer 2 interrupt INT5 | 180h F0h (SCALL 180h) Software interrupt (SW15) INT6 ↓ 1C0h F8h (SCALL 1C0h) External hardware interrupt, at any edge at BP50 or BP51 INT7 Highest 1E0h FCh (SCALL 1E0h) Voltage Monitor (VM) interrupt |
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Similar Description - ATAR090-C_14 |
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