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TSS461E Datasheet(PDF) 6 Page - ATMEL Corporation |
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TSS461E Datasheet(HTML) 6 Page - ATMEL Corporation |
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6 / 57 page  6 4194C–AUTO–01/06 TSS461E Microprocessor Interface The processor controls the TSS461E by reading and writing the internal registers of the circuit. These registers appear to the processor as regular memory locations. Interface Modes The TSS461E must be plugged in an Intel or Motorola environment with an 8-bit address/data bus multiplexed. Table 1. Access Mode Logic In Intel environment, access operations need CS active, a read one with RD active, a write one with WR active. If TSS461E is the single peripheral in the processor space, CS can be wired to VCC. In Motorola environment, the RD pin is wired to VSS and the access operations are driven by CS (E). Contrary to Intel mode, CS (E) must never be wired to Vcc even if the TSS461E is alone. To switch on-the-fly from one mode to the other, CS must be inactive. Intel Mode The Intel mode interface consists of 13 pins. 8 pins are the multiplexed address and data bus, and the rest are the address strobe, the read and write commands, the chip select and the inter- rupt request pins. To access the memory locations in Intel mode, the processor must first assert a valid address on the multiplexed address and data bus and drive the address strobe pin high. When the required set up time has passed, the processor must drive the address strobe low, and keep the address valid for the required hold time. The processor must then either assert the data to be written on the address and data bus, if a write is intended, or float the data bus for a read. The next step is to drive either the write or read command pins low, according to the function required, and at the same time drive the chip select pin high. The TSS461E access cycle is then terminated by driving the chip select and command pins low. Note: that the chip select pin may be driven high for the entire access cycle, and may also remain high during and after the termination of the cycle. CS (E) RD WR (R/W) Operation Mode 0 No operation 10 0 Write Operation in Motorola mode 10 1 Read operation in both modes 11 0 Write operation in Intel mode 11 1 No operation |
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