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AT86RF230 Datasheet(PDF) 3 Page - ATMEL Corporation

Part # AT86RF230
Description  Registers and Frame Buffer Accessible through Fast SPI
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT86RF230 Datasheet(HTML) 3 Page - ATMEL Corporation

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3
5131E-MCU Wireless-02/09
AT86RF230
3 General Circuit Description
This single-chip radio transceiver provides a complete radio transceiver interface
between the antenna and the microcontroller. It comprises the analog radio transceiver
and the digital demodulation including time and frequency synchronization, and data
buffering. The number of external components is minimized such that only an antenna,
a crystal and four decoupling capacitors are required. The bidirectional differential
antenna pins are used for transmission and reception, so that no external antenna
switch is needed.
The AT86RF230 block diagram is shown in Figure 3-1.
Figure 3-1.
Block Diagram of the AT86RF230
LNA
PPF
ADC
AGC
PA
Frequency
Synthesis
I
Q
SPI
Slave
Interface
TX power
control
TX Data
Limiter
5
RSSI
XOSC
Control Logic/
Configuration
Registers
CLKM
Fame
Buffer
TX BBP
RX BBP
SSBF
IRQ
SCLK
MISO
MOSI
SLP_TR
DCLK
RFP
RFN
Digital Domain
Analog Domain
DVREG
BATMON
AVREG
FTN
RST
SEL
The received RF signal at pins RFN and RFP is differentially fed through the low-noise
amplifier (LNA) to the RF filter (PPF) to generate a complex signal. This signal is
converted down by mixers to an intermediate frequency and fed to the integrated
channel filter (SSBF). The limiting amplifier provides sufficient gain to drive the
succeeding analog-to-digital converter (ADC) and generates a digital RSSI signal with
3 dB granularity. The ADC output signal is sampled by the digital base band receiver
(RX BBP).
The transmit modulation scheme is offset-QPSK (O-QPSK) with half-sine pulse shaping
and 32-length block coding (spreading) according to [1]. The modulation signal is
generated in the digital transmitter (TX BBP) and applied to the fractional-N frequency
synthesis (PLL) generating a coherent phase modulation required for demodulation of
O-QPSK signals. The frequency-modulated RF signal is fed to the power amplifier (PA).
An internal 128 byte RAM for RX and TX (Frame Buffer) buffers the data to be
transmitted or the received data. Two on chip low dropout (LDO) voltage regulators
provide the internal analog and digital 1.8V supply.


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