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HY29F040AC-15 Datasheet(PDF) 9 Page - Hynix Semiconductor |
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HY29F040AC-15 Datasheet(HTML) 9 Page - Hynix Semiconductor |
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9 / 40 page  9 HY29F040A writing the "set-up" command. Two more 'unlock' write cycles are then followed by the chip erase command. Upon executing the Chip Erase command sequence, the device’s internal state machine executes an internal erase algorithm. The system is not required to provide further controls or timings. The device will automatically provide adequate in- ternally generated erase pulses and verify chip erase within the proper cell margins. During chip erase, all sectors of the device are erased except protected sectors. During Chip Erase, data bit DQ7 shows a logical “0”. This operation is known as /Data Polling. The erase operation is completed when the data on DQ7 is a logical “1” (see Write Operation Status sec- tion). Upon completion of the Chip Erase operation, the device returns to read mode. At this time, the address pins are no longer latched. Note that /Data Polling must be performed at a sector address within any of the sectors being erased and not a protected sector to ensure that DQ7 returns a logical “1” upon completion of the Chip Erase operation. Figure 2 illustrates the Chip Erase Algorithm using typical command strings and bus operations. The device will ignore any commands written to the chip during execution of the internal Chip Erase algorithm. Sector Erase Command Sector erase is a six bus cycle operation (see Table 5). There are two 'unlock' write cycles that are fol- lowed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the sec- tor erase command. The sector address (any ad- dress location within the desired sector) is latched on the falling edge of /WE, while the command data is latched on the rising edge of /WE. An internal de- vice timer initiates Sector Erase operation after 100 m s ± 20% (80 ms to 120 ms) from the rising edge of the /WE pulse for the last Sector Erase command entered on the device. Upon executing the Sector Erase command sequence, the device’s internal state machine executes an internal erase algorithm. The system is not required to provide further controls or timings. The device will automatically provide adequate internally generated erase pulses and verify sector erase within the proper cell margins. Protected sectors of the device will not be erased, even if they are selected with the Sector Erase command. Multiple sectors can be erased sequentially by writ- ing the sixth bus cycle command of the Sector Erase command for each sector to be erased. The time between initiation of the next Sector Erase com- mand must be less than 80 ms to guarantee ac- ceptance of the command by the internal state ma- chine. The time-out window can be monitored via the write operation status pin DQ3 (refer to the Write Operation Status section for Sector Erase Timer operation). It is recommended that CPU interrupts be disabled during this time to ensure that the sub- sequent Sector Erase commands can be initiated within the 80 ms window. The interrupts can be re- enabled after the last Sector Erase command is written. As mentioned above, an internal device timer will initiate the Sector Erase operation 100 ms ± 20% (80 ms to 120 ms) from the rising edge of the last / WE pulse. The Sector Erase Timer Write Operation Status pin (DQ3) can be used to monitor the time out window. If another falling edge of the /WE occurs within the 100 ms time-out window, the internal de- vice timer is reset. Loading the sector erase buffer may be done in any sequence and with any num- ber of sectors. Any command other than Sector Erase or Erase Suspend or Erase Resume during this period and afterwards will reset the device to read mode, ig- noring the previous command string. Resetting the device after it has begun execution of a Sector Erase operation will result in the data in the oper- ated sectors being undefined. In this case, restart the Sector Erase operation on those sectors and allow them to complete the Erase operation. When erasing a sector or multiple sectors, the data in the unselected sectors remains unaffected. The system is not required to provide any controls or timings during these operations. |
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