HY628100ALT1 datasheet(3/9 Pages) HYNIX

Part #	HY628100ALT1

Description	128Kx8bit CMOS SRAM

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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HY628100A Series

Rev.05 /Feb.99

3

DC ELECTRICAL CHARACTERISTICS

Vcc = 5.0V

±10%, TA = 0°C to 70°C, unless otherwise specified

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

ILI

Input Leakage Current

Vss < VIN < Vcc

-1

-

1

uA

ILO

Output Leakage Current

Vss < VOUT < Vcc, /CS1 = VIH or

CS2 = VIL or /OE = VIH or /WE = VIL

-1

-

1

uA

Icc

Operating Power Supply

Current

/CS1 = VIL, CS2 = VIH,

VIN = VIH or VIL, II/O = 0mA

-

5

10

mA

ICC1

Average Operating

Current

/CS1 = VIL CS2 = VIH,

Min Duty Cycle = 100%, II/O = 0mA

-

30

50

mA

ISB

TTL Standby Current

(TTL Input)

/CS1 = VIH or CS2 = VIL

-

1

2

mA

ISB1

Standby Current

/CS1 > Vcc - 0.2V

-

1

mA

(CMOS Input)

CS2 > 0.2V or

L

-

2

100

uA

CS2 > Vcc - 0.2V

LL

-

1

20

uA

VOL

Output Low Voltage

IOL = 2.1Ma

-

0.4

V

VOH

Output High Voltage

IOH = -1mA

2.4

-

V

Note : Typical values are at Vcc = 5.0V, TA = 25

°C

AC CHARACTERISTICS

Vcc = 5.0V

±10%, TA = 0°C to 70°C (Normal), unless otherwise specified

-55

-70

-85

Min.

Max.

Min.

Max.

Min

Max.

1

TRC

Read Cycle Time

55

-

70

-

85

-

ns

2

tAA*

Address Access Time

-

55

-

70

-

85

ns

3

tACS*

Chip Select Access Time

-

55

-

70

-

85

ns

4

TOE

Output Enable to Output Valid

-

25

-

35

-

45

ns

5

TCLZ

Chip Select to Output in Low Z

10

-

10

-

10

-

ns

6

TOLZ

Output Enable to Output in Low Z

5

-

5

-

5

-

ns

7

tCHZ

Chip Deselection to Output in High Z

0

20

0

25

0

30

ns

8

tOHZ

Out Disable to Output in High Z

0

20

0

25

0

30

ns

9

tOH

Output Hold from Address Change

10

-

10

-

10

-

ns

10

tWC

Write Cycle Time

55

-

70

-

85

-

ns

11

tCW

Chip Selection to End of Write

45

-

60

-

70

-

ns

12

tAW

Address Valid to End of Write

45

-

60

-

70

-

ns

13

tAS

Address Set-up Time

0

-

0

-

0

-

ns

14

tWP

Write Pulse Width

40

-

50

-

55

-

ns

15

tWR

Write Recovery Time

0

-

0

-

0

-

ns

16

tWHZ

Write to Output in High Z

0

20

0

25

0

30

ns

17

tDW

Data to Write Time Overlap

25

-

30

-

35

-

ns

18

tDH

Data Hold from Write Time

0

-

0

-

0

-

ns

19

tOW

Output Active from End of Write

5

-

5

-

5

-

ns

Comment : tAA* and tACS* can meet 50ns with 30pF test load.

READ CYCLE

WRITE CYCLE

Symbol

Parameter

#

Unit

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