HYUNDAI ELECTRONICS AMERICA

HY62256A-I

32K x 8bit CMOS SRAM

TIMING INFORMATION

TIMING DIAGRAM

READ CYCLE 1

Note (READ CYCLE):

circuit conditions and are not referenced to output voltage levels.

both for a given device and from device to device.

3. /WE is high for the read cycle.

READ CYCLE 2

Note (READ CYCLE):

1. /WE is high for the read cycle.

WRITE CYCLE 1 (/OE Clocked)

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22/10/97 12:35

-sram/62256alt1

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