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ICS511-DPK Datasheet(PDF) 4 Page - Integrated Circuit Systems |
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ICS511-DPK Datasheet(HTML) 4 Page - Integrated Circuit Systems |
4 / 4 page LOCOTM PLL Clock Multiplier MDS 511 G 4 Revision 102504 In te gr at ed Circuit Syst ems ● 525 Ra ce St reet , San Jose, CA 9512 6 ● t e l (4 08) 297 -1 201 ● www.icst.com ICS511 DC Electrical Characteristics VDD=3.3 V ±5% , Ambient temperature -40 to +85 °C, unless stated otherwise AC Electrical Characteristics VDD = 3.3 V ±5%, Ambient Temperature -40 to +85 ° C, unless stated otherwise Note 1: Measured with 15 pF load. Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.135 3.465 V Input High Voltage, ICLK only VIH ICLK (pin 1) (VDD/2)+0.7 V Input Low Voltage, ICLK only VIL ICLK (pin 1) (VDD/2)-0.7 V Input High Voltage VIH OE (pin 7) 2.0 V Input Low Voltage VIL OE (pin 7) 0.8 V Input High Voltage VIH S0, S1 VDD-0.5 V Input Low Voltage VIL S0, S1 0.5 V Output High Voltage VOH IOH = -25 mA 2.4 V Output Low Voltage VOL IOL = 25 mA 0.4 V IDD Operating Supply Current, 20 MHz crystal No load, 100M 8 mA Short Circuit Current CLK output +70 mA On-Chip Pull-up Resistor Pin 7 270 k Ω Input Capacitance, S1, S0, and OE Pins 4, 6, 7 4 pF Nominal Output Impedance 20 Ω Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency, crystal input FIN 527 MHz Input Frequency, clock input FIN 250 MHz Output Frequency FOUT 0 °C to +70°C14 160 MHz -40 °C to +85°C14 145 MHz Output Clock Rise Time tOR 0.8 to 2.0 V, Note 1 1 ns Output Clock Fall Time tOF 2.0 to 8.0 V, Note 1 1 ns Output Clock Duty Cycle tOD 1.5 V, up to 160 MHz 45 49-51 55 % PLL Bandwidth 10 kHz Output Enable Time, OE high to output on 50 ns Output Disable Time, OE low to tri-state 50 ns Absolute Clock Period Jitter tja Deviation from mean +70 ps One Sigma Clock Period Jitter tjs 25 ps |
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