ICS580-01

Glitch-Free Clock Multiplexer

MDS 580-01 A

5

Revision 030300

Printed 11/28/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com

Parameter

Conditions

Minimum

Typical

Maximum

Units

ABSOLUTE MAXIMUM RATINGS

Supply voltage, VDD

Referenced to GND

7

V

Inputs and Clock Outputs

Referenced to GND

-0.5

VDD+0.5

V

Ambient Operating Temperature

0

70

°C

Ambient Operating Temperature, I version

Industrial temperature

-40

85

°C

Soldering Temperature

Max of 10 seconds

260

°C

Storage temperature

-65

150

°C

DC CHARACTERISTICS (VDDC = VDDI = 3.3 V unless noted)

DC CHARACTERISTICS (VDDC = VDDI = 3.3 V unless noted)

DC CHARACTERISTICS (VDDC = VDDI = 3.3 V unless noted)

Operating Voltage, VDDC

2.5

5.5

V

Operating Voltage, VDDI

VDDC

5.5

V

Input High Voltage, VIH, note 3

INA and INB only

(VDDC/2)+1 VDDC/2

VDDI

V

Input Low Voltage, VIL, note 3

INA and INB only

VDDC/2

(VDDC/2)-1

V

Input High Voltage, VIH

Non-clock inputs

2

VDDC

V

Input Low Voltage, VIL

Non-clock inputs

0.8

V

Output High Voltage, VOH

IOH=-12mA

VDDC-0.5

V

Output Low Voltage, VOL

IOL=12mA

0.5

V

Operating Supply Current, IDD

50 MHz inputs, no load

6

mA

Short Circuit Current

±70

mA

On-chip pull-up resistor, non-clock inputs

Pull-up to VDDC

250

k

Ω

Input Capacitance

4

pF

AC CHARACTERISTICS (VDDC = VDDI = 3.3 V unless noted)

AC CHARACTERISTICS (VDDC = VDDI = 3.3 V unless noted)

AC CHARACTERISTICS (VDDC = VDDI = 3.3 V unless noted)

Input Frequency, INA and INB. Note 1.

VDDC = 5 V

1/timeout

270

MHz

VDDC = 3.3 V

1/timeout

220

MHz

VDDC = 2.7 V

1/timeout

180

MHz

Propagation Delay, INA or INB to output

VDDC = 5 V

4

8

ns

VDDC = 3.3 V

5

10

ns

VDDC = 2.7 V

6

12

ns

Transition Detector Timeout, DIV=0

VDDI = 5 V

175

350

700

ns

VDDI = 3.3 V

500

1000

2000

ns

VDDI = 2.7 V

750

1500

3000

ns

Transition Detector Timeout, DIV=1

VDDI = 5 V

20

40

80

ns

VDDI = 3.3 V

55

110

210

ns

VDDI = 2.7 V

100

200

400

ns

Output Clock Rise Time

1.5

ns

Output Clock Fall Time

1.5

ns

Output Clock Skew, CLK1 to CLK2

Note 2

-250

0

250

ps

Electrical Specifications

Note 1. Frequencies less than the minimum may cause a timeout, which will not guarantee glitch-free switching unless the clock is

actually stopped.

Note 2. Assumes identically loaded outputs with identical rise times, measured at VDD/2.

Note 3. Output duty cycle is set by duty cycle of input clock at VDDC/2.