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ICS650R-01I Datasheet(PDF) 3 Page - Integrated Circuit Systems |
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ICS650R-01I Datasheet(HTML) 3 Page - Integrated Circuit Systems |
3 / 4 page ICS650-01 System Peripheral Clock Source MDS 650-01 C 3 Revision 092799 Printed 11/15/00 Integrated Circuit Systems • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • (408) 295-9818fax Parameter Conditions Minimum Typical Maximum Units ABSOLUTE MAXIMUM RATINGS (n note 1) Supply voltage, VDD Referenced to GND 7 V Inputs and Clock Outputs Referenced to GND -0.5 VDD+0.5 V Ambient Operating Temperature 0 70 C Soldering Temperature Max of 10 seconds 260 C Storage temperature -65 150 C DC CHARACTERISTICS (VDD = 3.3V V or 5V unless noted)) Operating Voltage, VDD 3.0 5.5 V Input High Voltage, VIH Select inputs, OE 2 V Input Low Voltage, VIL Select inputs, OE 0.8 V Output High Voltage, VOH VDD=3.3V, IOH=-8mA 2.4 V Output Low Voltage, VOL VDD=3.3V, IOL=8mA 0.4 V Output High Voltage, VOH, VDD = 3.3 or 5V IOH=-8mA VDD-0.4 V Operating Supply Current, IDD, at 5V No Load, note 2 50 mA Operating Supply Current, IDD, at 3.3V No Load, note 2 30 mA Short Circuit Current, VDD = 3.3 Each output ±50 mA Input Capacitance Except X1 7 pF AC CHARACTERISTICS (VDD = 3.3V V or 5V unless noted) Input Crystal or Clock Frequency 14.31818 MHz Output Clocks Accuracy (synthesis error) All clocks 1 ppm Output Clock Rise Time 0.8 to 2.0V 1.5 ns Output Clock Fall Time 2.0 to 0.8V 1.5 ns Output Clock Duty Cycle At VDD/2 40 50 60 % One Sigma Jitter, except ACLK 75 ps One Sigma Jitter, ACLK 170 ps Absolute Clock Period Jitter PCLK, UCLK, 20M - 500 500 ps Electrical Specifications Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability. 2. With all clocks at highest frequencies. External Components The ICS650 requires a minimum number of external components for proper operation. Decoupling capacitors of 0.1µF should be connected between VDD and GND (on pins 4 and 6, and pins 16 and 14), as close to the chip as possible. A series termination resistor of 33 Ω may be used for each clock output. The 14.31818 MHz crystal must be connected as close to the chip as possible. The crystal should be a fundamental mode, parallel resonant, 30ppm or better (to meet the Ethernet specs). Crystal capacitors should be connected from pins X1 to ground and X2 to ground. The value of these capacitors is given by the following equation, where CL is the crystal load capacitance: Crystal caps (pF) = (CL-12) x 2. So for a crystal with 16pF load capacitance, two 8pF caps should be used. If a clock input is used, drive it into X1 and leave X2 unconnected. |
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