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ICS8431CM-01 Datasheet(PDF) 8 Page - Integrated Circuit Systems |
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ICS8431CM-01 Datasheet(HTML) 8 Page - Integrated Circuit Systems |
8 / 11 page ICS8431CM-01 www.icst.com/products/hiperclocks.html REV. A JUNE 5, 2001 8 Integrated Circuit Systems, Inc. ICS8431-01 200MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER TERMINATION FOR PECL OUTPUTS The clock layout topology shown below is typical for IA64/32 platforms. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/PECL compatible outputs. Therefore, terminat- ing resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to FIGURE 5B. LVPECL OUTPUT TERMINATION 3.3V FOUT FIN 5 2 Zo Z o 5 2 Z o 3 2 Z o 3 2 Z o = 50Ω Z o = 50Ω Z o = 50Ω Z o = 50Ω FIGURE 5A. LVPECL OUTPUT TERMINATION RTT = 1 (VOH + VOL / VCC –2) –2 Z o Z o = 50Ω Z o = 50Ω 50 Ω 50 Ω RTT VCC-2V FIN FOUT Z o = 50Ω Z o = 50Ω FIGURE 6A. RECOMMENDED SCHEMATIC LAYOUT drive 50 Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and mini- mize signal distortion. There are a few simple termination schemes. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock lay- outs may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. LAYOUT GUIDELINE The schematic of the ICS8431-01 layout example used in this layout guideline is shown in Figure 6A. The ICS8431-01 recommended PCB board layout for this example is shown in Figure 6B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stacking of the P.C. board. R3 125 C3 0.01uF X1 U1 8431-01 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 28 27 26 25 nc nc nc nc nc nc nc nc nc SSC_CTL0 SSC_CTL1 VEE TEST_IO VDD VEE nFOUT FOUT VDDO nc nc VEE VDDA nc nc nc VDDI XTAL2 XTAL1 C1 0.1uF VDDA IN+ VDD IN- C4 10uF R4 84 R2 84 R1 50 IN+ VDD R2 50 R5 10 C6 0.01uF R3 50 R1 125 VDD TL2 Zo = 50 Ohm IN- VDD0 Termination A TL1 Zo = 50 Ohm C2 0.1uF Termination B (not shown in the layout) |
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