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ICS9112YG-16-T Datasheet(PDF) 5 Page - Integrated Circuit Systems |
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ICS9112YG-16-T Datasheet(HTML) 5 Page - Integrated Circuit Systems |
5 / 7 page 5 ICS9112-16 Output to Output Skew The skew between CLKOUT and the CLK(1-4) outputs is not dynamically adjusted by the PLL. Since CLKOUT is one of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded, zero phase difference will maintained from REF to all outputs. If applications requiring zero output-output skew, all the outputs must equally loaded. If the CLK(1-4) outputs are less loaded than CLKOUT, CLK(1-4) outputs will lead it; and if the CLK(1-4) is more loaded than CLKOUT, CLK(1-4) will lag the CLKOUT. Since the CLKOUT and the CLK(1-4) outputs are identical, they all start at the same time, but different loads cause them to have different rise times and different times crossing the measurement thresholds. REF input and all outputs loaded Equally REF input and CLK(1-4) outputs loaded equally, with CLKOUT loaded More. REF input and CLK(1_4) outputs loaded equally, with CLKOUT loaded Less. Timing diagrams with different loading configurations |
Similar Part No. - ICS9112YG-16-T |
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Similar Description - ICS9112YG-16-T |
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