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ICS9148-17 Datasheet(PDF) 6 Page - Integrated Circuit Systems |
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ICS9148-17 Datasheet(HTML) 6 Page - Integrated Circuit Systems |
6 / 15 page 6 ICS9148-17 Byte 3: SDRAMActive/Inactive Register (1 = enable, 0 = disable) t i B# n i PD W Pn o i t p i r c s e D 7 t i B8 21 ) t c a n I / t c A ( 7 M A R D S 6 t i B9 21 ) t c a n I / t c A ( 6 M A R D S 5 t i B1 31 ) t c a n I / t c A ( 5 M A R D S 4 t i B2 31 ) t c a n I / t c A ( 4 M A R D S 3 t i B4 31 ) t c a n I / t c A ( 3 M A R D S 2 t i B5 31 ) t c a n I / t c A ( 2 M A R D S 1 t i B7 31 ) t c a n I / t c A ( 1 M A R D S 0 t i B8 31 ) t c a n I / t c A ( 0 M A R D S Byte 4: SDRAM Active/Inactive Register (1 = enable, 0 = disable) Byte5:Peripheral Active/InactiveRegister (1 = enable, 0 = disable) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency selects will be Inverted logic level of the input frequency select pin conditions. t i B# n i PD W Pn o i t p i r c s e D 7 t i B- - # 0 S F d e h c t a L 6 t i B- 1 ) d e v r e s e R ( 5 t i B- 1 ) d e v r e s e R ( 4 t i B- 1 ) d e v r e s e R ( 3 t i B7 11 ) t c a n I / t c A ( 1 1 M A R D S ) y l n O e d o M p o t k s e D ( 2 t i B8 11 ) t c a n I / t c A ( 0 1 M A R D S ) y l n O e d o M p o t k s e D ( 1 t i B0 21 ) t c a n I / t c A ( 9 M A R D S 0 t i B1 21 ) t c a n I / t c A ( 8 M A R D S t i B# n i PD W Pn o i t p i r c s e D 7 t i B- - # 2 S F d e h c t a L 6 t i B- 1 ) d e v r e s e R ( 5 t i B- 1 ) d e v r e s e R ( 4 t i B7 41 ) t c a n I / t c A ( 1 P G A 3 t i B- 1 ) d e v r e s e R ( 2 t i B- 1 ) d e v r e s e R ( 1 t i B6 41 ) t c a n I / t c A ( 1 F E R 0 t i B2 1 ) t c a n I / t c A ( 0 F E R Byte 1: CPU,Active/Inactive Register (1 = enable, 0 = disable) Byte 2: PCIActive/Inactive Register (1 = enable, 0 = disable) t i B# n i PD W Pn o i t p i r c s e D 7 t i B- 0 t i b n o i s r e V 6 t i B- 1 ) d e v r e s e R ( 5 t i B- 1 ) d e v r e s e R ( 4 t i B- 1 ) d e v r e s e R ( 3 t i B0 41 ) t c a n I / t c A ( 3 K L C U P C 2 t i B1 41 ) t c a n I / t c A ( 2 K L C U P C 1 t i B3 41 ) t c a n I / t c A ( 1 K L C U P C 0 t i B4 41 ) t c a n I / t c A ( 0 K L C U P C t i B# n i PD W Pn o i t p i r c s e D 7 t i B- - # 1 S F d e h c t a L 6 t i B7 1 ) t c a n I / t c A ( F _ K L C I C P 5 t i B5 11 ) t c a n I / t c A ( 0 P G A 4 t i B4 11 ) t c a n I / t c A ( 4 K L C I C P 3 t i B2 11 ) t c a n I / t c A ( 3 K L C I C P 2 t i B1 11 ) t c a n I / t c A ( 2 K L C I C P 1 t i B0 11 ) t c a n I / t c A ( 1 K L C I C P 0 t i B8 1 ) t c a n I / t c A ( 0 K L C I C P |
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