2

ICS9150- 04

Pin Descriptions

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

2

IOAPIC2

OUT

IOAPIC clock output (14.318MHz) powered by VDDL1

CPU3.3#_2.5

IN

Indicates whether VDDL1 & VDDL2 are 3.3 or 2.5V. Output

buffer strength compensates for VDDL selection to maintain

CPU to SDRAM skew. High = 2.5V, Low = 3.3V. Has pull-up

to VDDL1, must use series resistor for 3.3 or 5V logic levels.

3

REF0

OUT

14.318 MHz reference clock outputs.

4, 10, 17, 23, 31, 34,

40, 47, 53

GND

PWR

Ground.

5

X1

IN

14.318MHz input. Has internal load cap, (nominal 33pF).

6X2

OUT

Crystal output. Has internal load cap (33pF) and feedback

resistor to X1

8

PCICLK_F

OUT

Free running BUS clock during PCI_STOP#=0.

IN

Latched frequency select input. Has pull-up to VDD2.

9

PCICLK0

OUT

BUS clock output

IN

Latched frequency select input. Has pull-up to VDD2.

11, 12,

13, 14

PCICLK (1:4)

OUT

BUS clock outputs.

27

SDATA

IN

28

SCLK

IN

30

24MHz

OUT

24MHz clock output for Super I/O or FD.

IN

Latched frequency select input. Has pull-up to VDD4.

29

48MHz

OUT

48MHz clock output for USB.

IN

Latched input for MODE select. Converts 2 outputs to power

management CPU_STOP# and PCI_STOP# when low. Has pull-

up to VDD4.

1, 7, 15, 20, 26, 37,

43

VDD2, VDD1,

VDD3, VDD4

PWR

Nominal 3.3V power supply, see power groups for function.

50, 56

VDDL2, VDDL1

PWR

CPU and IOAPIC clock buffer power supply, either 2.5 or 3.3V

nominal.

18, 19, 21, 22, 24,

25, 32, 33, 35, 36,

38, 39, 41, 42, 44, 45

SDRAM (0:15)

OUT

SDRAM clocks

55

IOAPIC0

OUT

IOAPIC clock output. (14.318 MHz) Poweredby VDDL1

46, 48, 49, 51, 52

CPUCLK (0:4)

OUT

CPU Output clocks. Powered by VDDL2 (60 or 66.6MHz)

54

IOAPIC1

OUT

IOAPIC clock output. (14.31818 MHz) Powered by VDDL1

CPU_STOP#

IN

Halts CPUCLK clocks at logic "0" level when low. (in mobile,

MODE=0)

16

PCICLK5

OUT

PCI BUS clock 5

PCI_STOP#

IN

Halts PCICLK (0:4) at logic "0" level when low. (in mobile,

MODE=0)

Notes:

1:

Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor

to program logic Hi to VDD or GND for logic low.