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ICS9159M-13 Datasheet(PDF) 2 Page - Integrated Circuit Systems |
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ICS9159M-13 Datasheet(HTML) 2 Page - Integrated Circuit Systems |
2 / 7 page 2 ICS9159-13 Pin Descriptions PIN NUMBER PIN NAME TYPE DESCRIPTION 1, 8, 14, 20, 26 VDD PWR Power for logic, CPU and fixed frequency output buffers. 2X1 IN XTAL or external reference frequency input. This input includes XTAL load capacitance and feedback bias for a 12 - 16 MHz crystal, nominally 14.31818 MHz. 3 X2 OUT XTAL output which includes XTAL load capacitance. 4, 11, 17, 23 GND PWR Ground for logic, CPU and fixed frequency output buffers. 6, 7, 9, 10, 24, 25 PCLK(0:3) OUT Processor clock outputs which are a multiple of the input reference frequency as shown in the table above. 13, 12 FS(0:1) IN Frequency multiplier select pins. See table above. These inputs have internal pull-up devices. 15, 16, 18, 19, 21, 22 BCLK(0:5) OUT Bus clock outputs are fixed at one half the PCLK frequency. 5 OEN IN OEN tristates all outputs when low. This input has an internal pull-up device. 28, 27 REF(0:1) OUT REF is a buffered copy of the crystal oscillator or reference input clock, nominally 14.31818 MHz. |
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