REV. 0

AD7751

–9–

Figure 7 shows two typical connections for Channel V2. The

first option uses a PT (potential transformer) to provide com-

plete isolation from the mains voltage. In the second option the

AD7751 is biased around the neutral wire and a resistor divider

is used to provide a voltage signal that is proportional to the line

voltage. Adjusting the ratio of Ra and Rb is also a convenient

way of carrying out a gain calibration on the meter.

660mV

Ra

Rb

VR

V2P

AGND

Rf

Rf

CT

NEUTRAL

PHASE

V2N

Cf

Cf

660mV

V2P

Rf

NEUTRAL

PHASE

V2N

Cf

Cf

NOTE:

Ra

Rf;

Rb + VR = Rf

Figure 7. Typical Connections for Channel 2

POWER SUPPLY MONITOR

The AD7751 contains an on-chip power supply monitor. The

If the supply is less than 4 V

± 5%, the AD7751 will be reset.

This is useful to ensure correct device start-up at power-up and

power-down. The power supply monitor has built in hysteresis

and filtering. This gives a high degree of immunity to false

triggering due to noisy supplies.

5V

4V

0V

INTERNAL

RESET

RESET

TIME

ACTIVE

RESET

Figure 8. On-Chip Power Supply Monitor

As can be seen from Figure 8 the trigger level is nominally set

at 4 V. The tolerance on this trigger level is about

±5%. The

power supply and decoupling for the part should be such that

± 5% as specified for

normal operation.

HPF and Offset Effects

Figure 9 shows the effect of offsets on the real power calcula-

tion. As can be seen from Figure 9 an offset on Channel 1 and

Channel 2 will contribute a dc component after multiplication.

Since this dc component is extracted by the LPF and used to

generate the real power information, the offsets will have con-

tributed a constant error to the real power calculation. This

problem is easily avoided by enabling the HPF (i.e., pin AC/

DC

is set logic high) in Channel 1. By removing the offset from at

least 1 channel no error component can be generated at dc by

the multiplication. Error terms at cos(

ωt) are removed by the

LPF and the Digital-to-frequency conversion—see Digital-to-

Frequency Conversion section.

Vt

V

I

t

I

VI

VI

VI

t

I

V

t

VI

t

OS

OS

OS

OS

OS

OS

cos

cos

cos

cos

cos

ωω

ωω

ω

×

+×

+×

( )

+

×

( )

2

2

2

V

I

DC COMPONENT (INCLUDING ERROR TERM)

IS EXTRACTED BY THE LPF FOR REAL

POWER CALCULATION

2

FREQUENCY – RAD/S

2

V

I

0

Figure 9. Effect of Channel Offsets on the Real Power

Calculation

The HPF in Channel 1 has an associated phase response that is

compensated for on-chip. The phase compensation is activated

when the HPF is enabled and is disabled when the HPF is not

activated. Figures 10 and 11 show the phase error between

channels with the compensation network activated. The AD7751

is phase compensated up to 1 kHz as shown. This will ensure

correct active harmonic power calculation even at low power

factors.