4

ICS9248-146

Third party brands and names are the property of their respective owners.

Byte 1: CPU, Active/Inactive Register

(1= enable, 0 = disable)

Byte 2: PCI, Active/Inactive Register

(1= enable, 0 = disable)

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

1

d

e

v

r

e

s

e

R

6

t

i

B-

1

d

e

v

r

e

s

e

R

5

t

i

B3

11

4

K

L

C

I

C

P

4

t

i

B2

11

3

K

L

C

I

C

P

3

t

i

B1

11

2

K

L

C

I

C

P

2

t

i

B0

11

1

K

L

C

I

C

P

1

t

i

B9

1

0

K

L

C

I

C

P

0

t

i

B8

1

F

_

K

L

C

I

C

P

Notes:

1. Inactive means outputs are held LOW and are disabled

from switching.

2. Latched Frequency Selects (FS#) will be inverted logic

load of the input frequency select pin conditions.

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

1

d

e

v

r

e

s

e

R

6

t

i

B1

21

z

H

M

8

4

_

4

2

5

t

i

B0

21

z

H

M

8

4

4

t

i

B6

21

2

1

M

A

R

D

S

3

t

i

B7

21

1

1

M

A

R

D

S

2

t

i

B8

21

0

1

M

A

R

D

S

1

t

i

B0

31

9

M

A

R

D

S

0

t

i

B1

31

8

M

A

R

D

S

Byte 4: SDRAM , Active/Inactive Register

(1= enable, 0 = disable)

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

X

)

k

c

a

b

d

a

e

R

(

3

S

F

6

t

i

B-

X

)

k

c

a

b

d

a

e

R

(

2

S

F

5

t

i

B-

X

)

k

c

a

b

d

a

e

R

(

1

S

F

4

t

i

B-

X

)

k

c

a

b

d

a

e

R

(

0

S

F

3

t

i

B2

1

1

F

E

R

2

t

i

B3

1

0

F

E

R

1

t

i

B7

11

1

K

L

C

P

G

A

0

t

i

B6

11

0

K

L

C

P

G

A

Byte 5: AGP, Active/Inactive Register

(1= enable, 0 = disable)

Byte 3: SDRAM, Active/Inactive Register

(1= enable, 0 = disable)

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B3

31

7

M

A

R

D

S

6

t

i

B4

31

6

M

A

R

D

S

5

t

i

B6

31

5

M

A

R

D

S

4

t

i

B7

31

4

M

A

R

D

S

3

t

i

B8

31

3

M

A

R

D

S

2

t

i

B0

41

2

M

A

R

D

S

1

t

i

B1

41

1

M

A

R

D

S

0

t

i

B2

41

0

M

A

R

D

S

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

1

8

4

_

4

2

l

e

S

)

z

H

M

8

4

:

0

,

z

H

M

4

2

:

1

(

6

t

i

B-

1

d

e

v

r

e

s

e

R

5

t

i

B-

1

d

e

v

r

e

s

e

R

4

t

i

B-

1

d

e

v

r

e

s

e

R

3

t

i

B7

41

0

K

L

C

U

P

C

2

t

i

B6

41

1

K

L

C

U

P

C

1

t

i

B5

41

2

K

L

C

U

P

C

0

t

i

B-

1

d

e

v

r

e

s

e

R