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ICS9248YF-97-T Datasheet(PDF) 11 Page - Integrated Circuit Systems |
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ICS9248YF-97-T Datasheet(HTML) 11 Page - Integrated Circuit Systems |
11 / 14 page 11 ICS9248-97 Power Management Features: Note: 1. LOW means outputs held static LOW as per latency requirement next page. 2. On means active. 3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs. # D PK L C U P C2 / U P CC I P A O I6 6 V 3I C PF _ I C P . F E R z H M 8 4 c s Os O C V 0W O LW O LW O LW O LW O LW O LW O LF F OF F O 1N ON ON ON ON ON ON ON ON O Power Management Requirements: Note: 1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes low/ high to the first valid clock comes out of the device. 2. Power up latency is when PWR_DWN# goes inactive (high to when the first valid clocks are dirven from the device. l a n g i Se t a t S l a n g i S y c n e t a L f o s e g d e g n i s i r f o . o N K L C I C P # D P ) n o i t a r e p o l a m r o n ( 1S m 3 ) n w o d r e w o p ( 0. x a m 2 |
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