ICS9250-08

Third party brands and names are the property of their respective owners.

Integrated

Circuit

Systems, Inc.

Block Diagram

Frequency Generator & Integrated Buffers for Celeron & PII/III™

9250-08 Rev H 10/8/99

Functionality

Pin Configuration

Recommended Application:

BX, Appollo Pro 133 type of chip set.

Output Features:

•

3 - CPUs @2.5V, up to 150MHz.

•

17 - SDRAM @ 3.3V, up to 150MHz.

•

7 - PCI @3.3V

•

2 - IOAPIC @ 2.5V

•

1 - 48MHz, @3.3V fixed.

•

1 - 24MHz @ 3.3V

•

2 - REF @3.3V, 14.318MHz.

Features:

•

Up to 150MHz frequency support

•

Support power management: CPU, PCI, stop and Power

down Mode form I

•

Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).

•

Uses external 14.318MHz crystal

Key Specifications:

•

CPU – CPU: <175ps

•

CPU – PCI: min = 1ns max = 4ns

•

PCI – PCI: <250ps

•

SDRAM - SDRAM: <500ps

56-Pin SSOP

* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs

** Internal Pull-down resistor of 240K to GND on indicated inputs.

VDDREF

*

REF1

*PCI_STOP/REF0

GND

X1

X2

VDDPCI

*MODE/PCICLK_F

**FS3/PCICLK0

GND

VDDPCI

BUFFERIN

SDRAM11

SDRAM10

VDDSDR

SDRAM9

SDRAM8

GND

SDRAM15

SDRAM14

GND

SDATA

SCLK

PCICLK1

PCICLK2

PCICLK3

PCICLK4

PCICLK5

FS2/

VDDLIOAPIC

IOAPIC0

IOAPIC_F

GND

CPUCLK_F

CPUCLK1

VDDLCPU

CPUCLK2

GND

CPU_STOP#

SDRAM_F

VDDSDR

SDRAM0

SDRAM1

GND

SDRAM2

SDRAM3

SDRAM4

SDRAM5

VDDSDR

SDRAM6

SDRAM7

GND

SDRAM12

SDRAM13

VDD48

24MHz/FS0*

48MHz/FS1*

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

{

I C

2

3

S

F2

S

F1

S

F0

S

F

U

P

C

)

z

H

M

(

)

z

H

M

(

K

L

C

I

C

P

1111

3

3

1)

4

/

U

P

C

(

3

.

3

3

111

0

4

2

1)

4

/

U

P

C

(

1

3

11

0

1

0

5

1)

4

/

U

P

C

(

5

.

7

3

11

00

0

4

1)

4

/

U

P

C

(

5

3

10

1

1

5

0

1)

3

/

U

P

C

(

5

3

10

10

0

1

1)

3

/

U

P

C

(

7

6

.

6

3

10

0

1

5

1

1)

3

/

U

P

C

(

3

3

.

8

3

1

000

0

2

1)

3

/

U

P

C

(

0

0

.

0

4

0

111

3

.

0

0

1)

3

/

U

P

C

(

3

4

.

3

3

01

1

0

3

3

1)

3

/

U

P

C

(

3

3

.

4

4

01

01

2

1

1)

3

/

U

P

C

(

3

3

.

7

3

01

0

0

3

0

1)

2

/

U

P

C

(

3

3

.

4

3

00

11

8

.

6

6)

2

/

U

P

C

(

0

4

.

3

3

00

1

0

3

.

3

8)

2

/

U

P

C

(

5

6

.

1

4

000

1

5

7)

2

/

U

P

C

(

5

.

7

3

0000

4

2

1)

2

/

U

P

C

(

3

3

.

1

4

CPU_STOP#

PCI_STOP#

PLL2

PLL1

Spread

Spectrum

48MHz

IOAPIC0

CPUCLK [2:1]

CPUCLK_F

IOAPIC_F

SDRAM [15:0]

SDRAM_F

PCICLK [5:0]

PCICLK_F

X1

X2

XTAL

OSC

PCI

CLOCK

DIVDER

STOP

STOP

÷2

STOP

STOP

POR

SDATA

SCLK

FS[3:0]

MODE

{

I C

2

Control

Logic

Config.

Reg.

REF [1:0]

24MHz

LATCH

1

2

2

16

66

4

BUFFERIN

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any

information being relied upon by the customer is current and accurate.