3

ICS9250-28

Power Down Waveform

Note

1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all

the output clocks are driven Low on their next High to Low tranistiion.

2. Power-up latency <3ms.

3. Waveform shown for 100MHz

Maximum Allowed Current

Clock Enable Configuration

#

D

PK

L

C

U

P

CM

A

R

D

SC

I

P

A

O

Iz

H

M

6

6K

L

C

I

C

P

,

F

E

R

z

H

M

8

4

c

s

Os

O

C

V

0W

O

LW

O

LW

O

LW

O

LW

O

LW

O

LF

F

OF

F

O

1N

ON

ON

ON

ON

ON

ON

ON

O

5

1

8

n

o

i

t

i

d

n

o

C

n

o

i

t

p

m

u

s

n

o

c

y

l

p

p

u

s

V

5

.

2

x

a

M

,

s

d

a

o

l

p

a

c

e

t

e

r

c

s

i

d

x

a

M

V

5

2

6

.

2

=

2

q

d

d

V

D

N

G

r

o

3

q

d

d

V

=

s

t

u

p

n

i

c

i

t

a

t

s

l

l

A

n

o

i

t

p

m

u

s

n

o

c

y

l

p

p

u

s

V

5

.

2

x

a

M

,

s

d

a

o

l

p

a

c

e

t

e

r

c

s

i

d

x

a

M

V

5

6

4

.

3

=

2

q

d

d

V

D

N

G

r

o

3

q

d

d

V

=

s

t

u

p

n

i

c

i

t

a

t

s

l

l

A

e

d

o

M

n

w

o

d

r

e

w

o

P

0

=

#

N

W

D

R

W

P

(

A

m

0

1A

m

0

1

z

H

M

6

6

e

v

i

t

c

A

l

l

u

F

0

1

0

=

]

0

:

2

[

S

F

A

m

0

7A

m

0

0

4

z

H

M

0

0

1

e

v

i

t

c

A

l

l

u

F

1

1

0

=

]

0

:

2

[

S

F

A

m

0

0

1A

m

0

0

4

z

H

M

3

3

1

e

v

i

t

c

A

l

l

u

F

1

1

1

=

]

0

:

2

[

S

F

A

m

0

3

1A

m

0

5

4