MK1574

Frame Rate Communications PLL

MDS 1574-01 D

3

Revision 011999

Printed 11/15/00

MicroClock Division of ICS • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•(408)295-9818fax

I C R O

Parameter

Conditions

Minimum

Typical

Maximum

Units

ABSOLUTE MAXIMUM RATINGS (Note 1)

ABSOLUTE MAXIMUM RATINGS (Note 1)

Supply Voltage, VDD

Referenced to GND

7

V

Inputs and Clock Outputs

-0.5

VDD+0.5

V

Ambient Operating Temperature

0

70

°C

Soldering Temperature

Max of 10 seconds

250

°C

Storage Temperature

-65

150

°C

DC CHARACTERISTICS (VDD = 5V unless noted)

DC CHARACTERISTICS (VDD = 5V unless noted)

Operating Voltage, VDD

3

5.5

V

Input High Voltage, VIH

2

V

Input Low Voltage, VIL

0.8

V

Output High Voltage

IOH=-4mA

VDD-0.4

V

Output High Voltage

IOH=-25mA

2.4

V

Output Low Voltage

IOL=25mA

0.4

V

Operating Supply Current, IDD

No Load, VDD=5.0V

15

mA

Short Circuit Current

Each output

±100

mA

Input Capacitance

7

pF

AC CHARACTERISTICS (VDD = 5V unless noted)

AC CHARACTERISTICS (VDD = 5V unless noted)

Input Frequency

8.0000

kHz

Output Clock Rise Time

0.8 to 2.0V

1.5

ns

Output Clock Fall Time

2.0 to 0.8V

1.5

ns

Output Clock Duty Cycle, High Time

At VDD/2

40

49 to 51

60

%

Absolute Clock Period Jitter

1

ns

Actual mean frequency error versus target, note 2

Any clock selection

0

0

ppm

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure

to levels above the operating limits but below the Absolute Maximums may affect device reliability.

2. All multipliers as shown in the table on page two are exact, and are stored in ROM on the chip.

External Components/Crystal Selection

Electrical Specifications

The MK1574 requires a minimum number of external components for proper operation. An RC network

(see Capacitor Selection on following page) should be connected between CAP1 and CAP2 as close to the

chip as possible. A high quality ceramic capacitor is recommended. A decoupling capacitor of 0.1µF must

be connected between VDD and GND pins (pins 2 and 3, 5 and 7) close to the chip, and 33

Ω terminating

resistors can be used on clock outputs with traces longer than 1 inch.