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MK74CB115RTR Datasheet(PDF) 3 Page - Integrated Circuit Systems |
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MK74CB115RTR Datasheet(HTML) 3 Page - Integrated Circuit Systems |
3 / 5 page MK74CB115 1 to 16 Buffalo™ Clock Driver MDS 74CB115 D 3 Revision 020800 Printed 11/16/00 Integrated Circuit Systems, Inc. • 525 Race St. • San Jose • CA • 95126 • (408) 295-9800tel • www.icst.com Parameter Conditions Minimum Typical Maximum Units ABSOLUTE MAXIMUM RATINGS (Note 1) ABSOLUTE MAXIMUM RATINGS (Note 1) Supply Voltage, VDD Referenced to GND 7 V Inputs Referenced to GND 0.5 VDD+0.5 V Clock Outputs Referenced to GND 0.5 VDD+0.5 V Ambient Operating Temperature 0 70 °C Soldering Temperature Max of 20 seconds 260 °C Storage Temperature -65 150 °C DC CHARACTERISTICS (VDD = 3.3 V unless noted) DC CHARACTERISTICS (VDD = 3.3 V unless noted) Operating Voltage, VDD 3.0 3.3 5.5 V Input High Voltage, VIH (IN pin) Input clock (VDD/2)+1 VDD/2 V Input Low Voltage, VIL (IN pin) Input clock VDD/2 (VDD/2)-1 V Input High Voltage, VIH (OE pins) 2.0 V Input Low Voltage, VIL (OE pins) 0.8 V Output High Voltage, 3.3V IOH=-8mA VDD-0.4 V Output High Voltage, 3.3V IOH=-12mA 2.4 V Output Low Voltage, 3.3V IOL=12mA 0.8 V Operating Supply Current, IDD, at 100 MHz No Load 55 mA Output Impedance 14 Ω Short Circuit Current, 3.3V Each output ±50 mA On-Chip Pull-up Resistor OE0, OE1, OE2 250 k Ω Input Capacitance 5 pF AC CHARACTERISTICS (VDD = 3.3 V unless noted) AC CHARACTERISTICS (VDD = 3.3 V unless noted) Input Clock Frequency with load = 8 pF Note 4, 5 0 200 MHz Propagation Delay with load = 15pF 1.4 3 ns Output Clock Rise Time 0.8 to 2.0V 2 ns Output Clock Fall Time 2.0 to 0.8V 2 ns Output Clock Rising Edge Skew At VDD/2. Note 2 100 250 ps Output Enable Time, OE high to output on 20 ns Output Disable Time, OE low to tri-state 20 ns Electrical Specifications Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability. 2. Between any two outputs, with equal loading. 3. At VDD = 3.3 V, 70°C, series termination of 33 Ω per pin , 8 pF load per pin. 4. See discussion and graph of speed versus load, Graph 1 on following page. |
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