6.10

4

IDT 70121/70125S/L

HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT

COMMERCIAL TEMPERATURE RANGE

70121L/70125L

Symbol

Parameter

Test Condition

Min.

Typ.

(1)

Max.

Unit

2

—

—

V

Data Retention Current

Com’l.

—

100

1500

µA

(3)

Chip Deselect to Data Retention Time

0

—

—

ns

(3)

Operation Recovery Time

(2)

——

ns

NOTES:

2654 tbl 06

°C, and are not production tested.

3. This parameter is guaranteed by device characterization but is not production tested.

DATA RETENTION WAVEFORM

2V

≥

DATA RETENTION MODE

Vcc

CE

4.5V

4.5V

2654 drw 03

AC ELECTRICAL CHARACTERISTICS OVER THE

70121X25

70121X35

70121X45

70121X55

70125X25

70125X35

70125X45

70125X55

Symbol

Parameter

Min. Max. Min. Max. Min. Max. Min. Max. Unit

Read Cycle

Read Cycle Time

25

—

35

—

45

—

55

—

ns

Address Access Time

—

25

—

35

—

45

—

55

ns

Chip Enable Access Time

—

25

—

35

—

45

—

55

ns

Output Enable Access Time

—

12

—

25

—

30

—

35

ns

Output Hold from Address Change

0

—

0

—

0

—

0

—

ns

Output Low-Z Time

(1,2)

0—

0

—

0—

0

—

ns

Output High-Z Time

(1,2)

—10

—

15

—20

—

30

ns

Chip Enable to Power-Up Time

(2)

0—

0

—

0—

0

—

ns

Chip Disable to Power-Down Time

(2)

—50

—

50

—50

—

50

ns

NOTES:

2654 tbl 08

1. Transition is measured

±500mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. This parameter guaranteed by device characterization, but is not production tested.

3. “X” in part numbers indicates power rating (S or L).

AC TEST CONDITIONS

Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

5ns

Input Timing Reference Levels

1.5V

Output Reference Levels

1.5V

Output Load

Figures 1 and 2

2654 tbl 07

1250

Ω

30pF

775

Ω

BUSY

INT

5V

5V

1250

Ω

5pF

775

Ω

2654 drw 04

Figure 1. AC Output Test Load

Figure 2. Output Test Load

(

Including scope and jig.