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IDT6116LA55DB Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT6116LA55DB Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 11 page 6.42 IDT6116SA/LA CMOS Static RAM 2K (16K x 8-Bit) Military, Commercial, and In dustrial Temperature Ranges 9 Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,5,7) Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,2,3,5,7) NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 4. During this period, the I/O pins are in the output state and the input signals must not be applied. 5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state. 6. Transition is measured ±500mV from steady state. 7. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse is the specified tWP. For a CS controlled write cycle, OE may be LOW with no degradation to tCW. ADDRESS DATAOUT CS WE DATAIN tWC tAW 3089 drw 09 tAS tWHZ (6) (4) tDW tDH (4) tOW tWR tCHZ (6) tWP(7) (6) PREVIOUS DATA VALID DATA VALID DATA VALID (3) , CS WE DATAIN tWC tAW tCW tWR (3) tDW tDH tAS 3089 drw 10 DATA VALID ADDRESS , |
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