Low-Power, SOT µP Reset Circuit with

SGM800

Capacitor-Adjustable Reset Timeout Delay

8

SG Micro Corp

www.sg-micro.com

APPLICATION INFORMATION

Interfacing

to

Other

Voltages

for

Logic

Compatibility

The open-drain output of the SGM800 can be used to

interface to µPs with other logic levels. As shown in

Figure 1, the open-drain output can be connected to

voltages from 0 to 5.5V. This allows for easy logic

compatibility to various µPs.

+

-

3.3V

RESET

TIMEOUT

RESET

SRT

GND

SGM800

5.0V

10k

Ω

5V

SYSTEM

Supplies

In addition to issuing a reset to the µP during power-up,

power-down, and brownout conditions, this supervisor is

relatively immune to short-duration negative-going

transients (glitches). The graph Maximum Transient

Duration vs. Reset Threshold Overdrive in the Typical

Performance Characteristics shows this relationship.

The area below the curve of the graph is the region in

which these devices typically do not generate a reset

pulse. This graph was generated using a negative-going

indicated (reset-threshold overdrive). As the magnitude

of the transient decreases (further below the reset

threshold), the maximum allowable

pulse

width-

below the reset threshold and lasts 50µs or less does not

cause a reset pulse to be issued.

Wired-OR Reset

To allow auxiliary circuitry to hold the system in reset, an

external open-drain logic signal can be connected to the

2. This configuration can reset the µP, but does not

provide the reset timeout when the external logic signal is

released.

RESET

μP

RESET

OPEN-DRAIN

LOGIC

N

N

10k

Ω

GND

SGM800

Figure 2. Wired-OR Reset Circuit

Layout Consideration

SRT is a precise current source. When developing the

layout for the application, be careful to minimize board

capacitance and leakage currents around this pin. Traces

connected to SRT should be kept as short as possible.

Traces carrying high-speed digital signals and traces with

large voltage potentials should be routed as far from SRT

as possible. Leakage current and stray capacitance (e.g.,

a scope probe) at this pin could cause errors in the reset

timeout period. When evaluating these parts, use clean

prototype boards to ensure accurate reset periods.