11.1

4

IDT6178S

CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGE

CYCLE DESCRIPTION

Match Cycle: A match cycle occurs when all control signals

(

OE, WE, CLR) are HIGH. At that time, data supplied to the

RAM on the I/O pins is compared with the data stored at the

specified address. The totem-pole match output is HIGH

when there is a match at all data bits, and drives LOW if there

is not a match.

Write Cycle: The write cycle is conventional, occuring when

WE is LOW and CLR is HIGH. OE may be either HIGH or LOW,

since it is overridden by

WE. The state of the Match pin is not

guaranteed, but in the current implementation it continues to

reflect the output of the comparator. The Match pin goes

HIGH during write cycles since the data at the specified

address is the same as the data (being written) at the I/Os of

the RAM.

Read Cycle: When

WE and CLR are HIGH and OE is LOW,

the RAM is in a read cycle. The state of the Match pin is not

guaranteed, but in the current implementation it continues to

reflect the output of the comparator. The Match pin goes

HIGH during read cycles since the data at the specified

address is the same as the data (being read) at the I/Os of the

RAM.

Clear Cycle: When

CLR is asserted, every bit in the RAM is

cleared to zero. If

OE is LOW during a clear cycle, the RAM

I/Os will be driven. However, this data is not necessarily

zeros, even after a considerable time. The Match pin is

enabled, but its state is not predicable.

NOTE:

1. It is not recommended to let address and data input pins float while MATCH pin is active.

TIMING WAVEFORM OF MATCH CYCLE

(1)

± 10%, All Temperature Ranges)

6178S10

(1)

6178S12

6178S15

6178S20

6178S25

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Match Cycle

Address to Match Valid

—

10

—

12

—

15

—

20

—

25

ns

Data Input to Match Valid

—

8

—

11

—

13

—

15

—

15

ns

Match Valid Hold from

OE

0

—

0—

0

—

0

—

0—

ns

OE HIGH to Match Valid

—

10

—

12

—

15

—

20

—

20

ns

Match Valid Hold from

WE

0

—

0—

0

—

0

—

0—

ns

WE HIGH to Match Valid

—

10

—

12

—

15

—

20

—

20

ns

Match Valid Hold from

CLR

0

—

0—

0

—

0

—

0—

ns

Match Valid Hold from Address

3

—

3

—

3

—

3

—

3

—

ns

Match Valid Hold from Data

3

—

3

—

3

—

3

—

3

—

ns

NOTE:

2953 tbl 10

1. 0

°C to +70°C temperature range only.

2953 drw 07

OE

ADDRESS

WE

CLR

MATCH

MATCH VALID

MATCH

MATCH

NO MATCH