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IDT70824L35G Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT70824L35G Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 21 page  6.07 APRIL 2000 DSC-3099/5 1 ©2000 Integrated Device Technology, Inc. HIGH SPEED 64K (4K X 16 BIT) SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAM™) Functional Block Diagram IDT70824S/L Features x x x x x High-speed access – Military: 35/45ns (max.) – Commercial: 20/25/35/45ns (max.) x x x x x Low-power operation – IDT70824S Active: 775mW (typ.) Standby: 5mW (typ.) – IDT70824L Active: 775mW (typ.) Standby: 1mW (typ.) x x x x x 4K x 16 Sequential Access Random Access Memory (SARAM™) – Sequential Access from one port and standard Random Access from the other port – Separate upper-byte and lower-byte control of the Random Access Port x x x x x High speed operation – 20ns tAA for random access port – 20ns tCD for sequential port – 25ns clock cycle time x x x x x Architecture based on Dual-Port RAM cells x x x x x Compatible with Intel BMIC and 82430 PCI Set x x x x x Width and Depth Expandable x x x x x Sequential side – Address based flags for buffer control – Pointer logic supports up to two internal buffers x x x x x Battery backup operation - 2V data retention x x x x x TTL-compatible, single 5V (+10%) power supply x x x x x Available in 80-pin TQFP and 84-pin PGA x x x x x Military product compliant to MIL-PRF-38535 QML x x x x x Industrial temperature range (–40°C to +85°C) is available for selected speeds Description TheIDT70824isahigh-speed4Kx16-BitSequentialAccessRandom Access Memory (SARAM). The SARAM offers a single-chip solution to buffer data sequentially on one port, and be accessed randomly (asyn- chronously) through the other port. The device has a Dual-Port RAM based architecture with a standard SRAM interface for the random (asynchronous) access port, and a clocked interface with counter se- Random Access Port Controls Sequential Access Port Controls 4KX16 Memory Array DataL DataR AddrL AddrR I/O0-15 SI/O0-15 Pointer/ Counter 12 Start Address for Buffer #1 End Address for Buffer #1 Start Address for Buffer #2 End Address for Buffer #2 Flow Control Buffer Flag Status EOB1 EOB2 12 12 12 16 12 12 RST COMPARATOR LB UB A0-11 12 CE OE R/ W LSB MSB CMD 16 RST SCLK CNTEN SOE SSTRT2 SCE SR/ W SLD SSTRT1 16 12 3099 drw 01 Reg. , |
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