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IDT70825L45G Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT70825L45G Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 21 page 6.31 6 IDT70825S/L HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES DATA RETENTION MODE VCC CE 3016 drw 04 4.5V tCDR tR VDR VIH 4.5V VDR 2V ≥ SCLK SCE VIH ICC ISB tPD ISB tPU NOTES : 1. SCE is synchronized to the sequential clock input. 2. CMD > VCC - 0.2V. DATA RETENTION AND POWER DOWN/UP WAVEFORM (RANDOM AND SEQUENTIAL PORT) (1,2) Figure 3. Lumped Capacitance Load Typical Derating Curve 1 2 3 4 5 6 7 8 20 40 60 80 100 120 140 160 180 200 CAPACITANCE (pF) 10pF is the I/O capacitance of this device, and 30pF is the AC Test Load capacitance. 3016 drw 07 tAA/tCD/tEB (Typical, ns) -1 -2 -3 3016 drw 06 893 Ω 30pF 347 Ω 5V DATAOUT 893 Ω 5pF 347 Ω 5V DATAOUT 3016 drw 05 Figure 2. Output Test Load (for tCLZ, tBLZ, tOLZ, tCHZ, tBHZ, tOHZ, tWHZ, tCKHZ, and tCKLZ) Including scope and jig. Figure 1. AC Output Test Load AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Max. Input Timing Reference Levels 1.5V Output Reference Levels 1.5V AC Test Load Figures 1, 2, and 3 3016 tbl 10 |
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