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IDT70V24L35G Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT70V24L35G Datasheet(HTML) 9 Page - Integrated Device Technology |
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9 / 17 page  6.38 9 IDT70V24S/L HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1) TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4) NOTES: 1. D0R = D0L = VIL, CER = CEL = VIH, or Both UB & LB = VIH Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start. 2. “A” may be either left or right port. “B” is the opposite port from “A”. 3. This parameter is measured from R/ WA or SEMA going High to R/WB or SEMB going High. 4. If tSPS is not satisfied there is no guarantee which side will be granted the semaphore flag. NOTES: 1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle). 2. "DATAOUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value. SEM"A" 2911 drw 11 tSPS MATCH R/ W"A" MATCH A0"A"-A2"A" SIDE “A” (2) SEM"B" R/ W"B" A0"B"-A2"B" SIDE (2) “B” SEM 2911 drw 10 tAW tEW tSOP I/O0 VALID ADDRESS tSAA R/ W tWR tOH tACE VALID ADDRESS DATAIN VALID DATAOUT tDW tWP tDH tAS tSWRD tAOE Read Cycle Write Cycle A0-A2 OE VALID(2) |
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