6.38

6

IDT70V24S/L

HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM

COMMERCIAL TEMPERATURE RANGE

AC TEST CONDITIONS

Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

5ns Max.

Input Timing Reference Levels

1.5V

Output Reference Levels

1.5V

Output Load

Figures 1 and 2

2911 tbl 10

Figure 1. Output Test Load

Figure 2. Output Test Load

* Including scope and jig.

2911 drw 05

590

Ω

30pF

435

Ω

3.3V

BUSY

INT

590

Ω

5pF

435

Ω

3.3V

AC ELECTRICAL CHARACTERISTICS OVER THE

IDT70V24X25

IDT70V24X35

IDT70V24X55

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

READ CYCLE

Read Cycle Time

25

—

35

—

55

—

ns

Address Access Time

—

25

—

35

—

55

ns

Chip Enable Access Time

(3)

—25

—

35

—55

ns

Byte Enable Access Time

(3)

—25

—

35

—55

ns

Output Enable Access Time

—

15

—

20

—

30

ns

Output Hold from Address Change

3

—

3

—

3

—

ns

Output Low-Z Time

(1, 2)

3

—

3—

3—

ns

Output High-Z Time

(1, 2)

—15

—

20

—25

ns

Chip Enable to Power Up Time

(2)

0

—

0—

0—

ns

Chip Disable to Power Down Time

(2)

—25

—

35

—50

ns

Semaphore Flag Update Pulse (

OE or SEM)15

—

15

—

15

—

ns

Semaphore Address Access Time

—

35

—

45

—

65

ns

NOTES:

2911 tbl 11

1. Transition is measured

±200mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM,

4. "X" in part numbers indicates power rating (S or L).

TIMING OF POWER-UP POWER-DOWN

CE

2911 drw 06

50%

50%