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IDT70825S25PFB Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT70825S25PFB Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 21 page IDT70825S/L HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES 6.31 9 CASE 5: BUFFER FLOW MODES Within the SARAM, the user can designate one of four buffer flow modes for each buffer. Each buffer flow mode defines a unique set of actions for the sequential port address pointer and EOB flags. In BUFFER CHAINING mode, after the address pointer reaches the end of the buffer, it sets the corresponding EOB flag and continues from the start address of the other buffer. In STOP mode, the address pointer stops incrementing after it reaches the end of the buffer. In LINEAR mode, the address pointer ignores the end of buffer address and increments past it, but sets the EOB flag. MASK mode is the same as LINEAR mode except EOB flags are not set. CASES 1 THROUGH 4: START AND END OF BUFFER REGISTER DESCRIPTION(1,2) 15 MSB LSB I/O BITS 3016 drw 10 H H 12 ------------------------------------------------------------------------------------------------------------ Address Loaded into Buffer 0 14 13 H reading and clearing the status of the EOB flags. Seven different CMD cases are available depending on the condi- tions of A0-A2 and R/W. Address bits A3-A12 and data I/O bits I/O13-I/O15 are not used during this operation. RANDOM ACCESS PORT CMD CMD CMD CMD CMD MODE(1) Case # A2-A0 R/ W W W W W DESCRIPTIONS 1 000 0 (1) Write (read) the start address of Buffer #1 through I/O0-I/O12. 2 001 0 (1) Write (read) the end address of Buffer #1 through I/O0-I/O12. 3 010 0 (1) Write (read) the start address of Buffer #2 through I/O0-I/O12. 4 011 0 (1) Write (read) the end address of Buffer #2 through I/O0-I/O12. 5 100 0 (1) Write (read) flow control register 6 101 0 Write only – clear EOB1 and/or EOB2 flag 7 101 1 Read only – flag status register 8 110/111 (X) (Reserved) NOTE: 1. R/ W input "0(1)" indicates a write(0) or read(1) occurring with the same address input. 3016 tbl 16 Register Contents Address Pointer 0 EOB Flags Cleared to High state Buffer Flow Mode BUFFER CHAINING Start Address Buffer #1 0 (1) End Address Buffer #1 4095 (4K) Start Address Buffer #2 4096 (4K+1) End Address Buffer #2 8191 (8K) Registered State SCE = VIH, SR/W = VIL 3016 tbl 15 Reset ( RST RST RST RST RST) Setting RST LOW resets the control state of the SARAM. RST functions asynchronously of SCLK, (i.e. not registered). The default states after a reset operation are as follows: BUFFER COMMAND MODE ( CMD CMD CMD CMD CMD) Buffer Command Mode ( CMD) allows the random access port to control the state of the two buffers. Address pins A0-A2 and I/O pins I/O0-I/O12 are used to access the start of buffer and the end of buffer addresses and to set the flow control mode of each buffer. The Buffer Command Mode also allows NOTES: 1. "H" = VOH for I/O in the output state and "Don't Cares" for I/O in the input state. 2. A write into the buffer occurs when R/ W = VIL and a read when R/W = VIH. EOB1/SOB1 and EOB2/SOB2 are chosen through address A0-A2 while CMD = VIL and CE = VIH. |
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