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IDT70V07L35J Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT70V07L35J Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 18 page 6.37 6 IDT70V07S/L HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Max. Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load Figures 1 and 2 2943 tbl 10 Figure 1. AC Output Test Load Figure 2. Output Test Load (for tLZ, tHZ, tWZ, tOW) * Including scope and jig. 2943 drw 06 590 Ω 30pF 435 Ω 3.3V DATAOUT BUSY INT 590 Ω 5pF 435 Ω 3.3V DATAOUT 2943 drw 05 CE 2943 drw 07 tPU ICC ISB tPD 50% 50% TIMING OF POWER-UP POWER-DOWN NOTES: 2943 tbl 11 1. Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. 4. "X" in part numbers indicates power rating (S or L). AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4) IDT70V07X25 IDT70V07X35 IDT70V07X55 Symbol Parameter Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 25 — 35 — 55 — ns tAA Address Access Time — 25 — 35 — 55 ns tACE Chip Enable Access Time (3) —25 — 35 — 55 ns tAOE Output Enable Access Time — 15 — 20 — 30 ns tOH Output Hold from Address Change 3 — 3 — 3 — ns tLZ Output Low-Z Time (1, 2) 3— 3 — 3 — ns tHZ Output High-Z Time (1, 2) —15 — 20 — 25 ns tPU Chip Enable to Power Up Time (2) 0— 0 — 0 — ns tPD Chip Disable to Power Down Time (2) —25 — 35 — 50 ns tSOP Semaphore Flag Update Pulse ( OE or SEM)15 — 15 — 15 — ns tSAA Semaphore Address Access Time — 35 — 45 — 65 ns |
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