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IDT7024S17G Datasheet(PDF) 11 Page - Integrated Device Technology |
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IDT7024S17G Datasheet(HTML) 11 Page - Integrated Device Technology |
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11 / 20 page  IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES 6.15 11 TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1) NOTES: 1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle). 2. "DATAOUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value. NOTES: 1. D0R = D0L = VIL, CER = CEL = VIH, or both UB & LB = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start. 2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 3. This parameter is measured from R/ WA or SEMA going High to R/WB or SEMB going High. 4. If tSPS is not satisfied, there is no guarantee which side will be granted the Semaphore flag. TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4) SEM"A" 2740 drw 12 tSPS MATCH R/ W"A" MATCH A0"A"-A2"A" SIDE “A” (2) SEM"B" R/ W"B" A0"B"-A2"B" SIDE (2) “B” SEM 2740 drw 11 tAW tEW tSOP I/O0 VALID ADDRESS tSAA R/ W tWR tOH tACE VALID ADDRESS DATAIN VALID DATAOUT tDW tWP tDH tAS tSWRD tAOE Read Cycle Write Cycle A0-A2 OE VALID(2) |
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