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IDT7027L25GB Datasheet(PDF) 7 Page - Integrated Device Technology

Part # IDT7027L25GB
Description  HIGH-SPEED 32K x 16 DUAL-PORT STATIC RAM
Download  19 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT7027L25GB Datasheet(HTML) 7 Page - Integrated Device Technology

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6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
7
AC Test Conditions
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Ranges(4,6)
NOTES:.
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM,
CE = VIL and SEM = VIH. To access semaphore, CE= VIH and SEM = VIL.
4. 'X' in part numbers indicates power rating (S or L).
5. Refer to Chip Enable Truth Table.
6. Industrial temperature: for other speeds, packages and powers contact your sales office.
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
*Including scope and jig.
dInput Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns Max.
1.5V
1.5V
Figures 1 and 2
3199 tbl 11
3199 drw 04
893
30pF
347
5V
DATAOUT
BUSY
INT
893
5pF*
347
5V
DATAOUT
7027X20
Com'l Only
7027X25
Com'l, Ind.
& Military
7027X35
Com'l &
Military
7027X55
Com'l &
Military
Symbol
Parameter
Min.Max.Min.
Max.Min.
Max.Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
20
____
25
____
35
____
55
____
ns
tAA
Address Access Time
____
20
____
25
____
35
____
55
ns
tACE
Chip Enable Access Time
(3)
____
20
____
25
____
35
____
55
ns
tABE
Byte Enable Access Time
(3)
____
20
____
25
____
35
____
55
ns
tAOE
Output Enable Access Time
____
12
____
13
____
20
____
30
ns
tOH
Output Hold from Address Change
3
____
3
____
3
____
3
____
ns
tLZ
Output Low-Z Time
(1,2)
3
____
3
____
3
____
3
____
ns
tHZ
Output High-Z Time
(1,2)
____
12
____
15
____
15
____
25
ns
tPU
Chip Enable to Power Up Time
(2,5)
0
____
0
____
0
____
0
____
ns
tPD
Chip Disable to Power Down Time(2,5)
____
20
____
25
____
35
____
50
ns
tSOP
Semaphore Flag Update Pulse (
OE or SEM)10
____
12
____
15
____
15
____
ns
tSAA
Semaphore Address Access Time
____
20
____
25
____
35
____
55
ns
3199 tbl 12


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