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IDT71256SA12PZ Datasheet(PDF) 4 Page - Integrated Device Technology |
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IDT71256SA12PZ Datasheet(HTML) 4 Page - Integrated Device Technology |
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4 / 8 page  4 IDT71256SA CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges AC Electrical Characteristics (VCC = 5.0V ± 10%) NOTE: 1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested. Symbol Parameter 71256SA12 71256SA15 71256SA20 71256SA25 Unit Min. Max. Min. Max. Min. Max. Min. Max. Read Cycle tRC Read Cycle Time 12 ____ 15 ____ 20 ____ 25 ____ ns tAA Address Access Time ____ 12 ____ 15 ____ 20 ____ 25 ns tACS Chip Select Access Time ____ 12 ____ 15 ____ 20 ____ 25 ns tCLZ(1) Chip Select to Output in Low-Z 4 ____ 4 ____ 4 ____ 4 ____ ns tCHZ(1) Chip Sele ct to Output in High-Z 0 6070 10 0 11 ns tOE Output Enable to Output Valid ____ 6 ____ 7 ____ 10 ____ 11 ns tOLZ(1) Output Enab le to Output in Low-Z 0 ____ 0 ____ 0 ____ 0 ____ ns tOHZ(1) Output Disab le to Output in High-Z 0 60608 0 10 ns tOH Output Hold from Address Change 3 ____ 3 ____ 3 ____ 3 ____ ns tPU(1) Chip Sele ct to Power Up Time 0 ____ 0 ____ 0 ____ 0 ____ ns tPD(1) Chip Deselect to Power Down Time ____ 12 ____ 15 ____ 20 ____ 25 ns Write Cycle tWC Write Cycle Time 12 ____ 15 ____ 20 ____ 25 ____ ns tAW Address Valid to End-of-Write 9 ____ 10 ____ 15 ____ 20 ____ ns tCW Chip Select to End-of-Write 9 ____ 10 ____ 15 ____ 20 ____ ns tAS Address Set-up Time 0 ____ 0 ____ 0 ____ 0 ____ ns tWP Write Pulse Width 8 ____ 10 ____ 15 ____ 20 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 6 ____ 7 ____ 11 ____ 13 ____ ns tDH Data Hold Time 0 ____ 0 ____ 0 ____ 0 ____ ns tOW(1) Output Active from End-of-Write 4 ____ 4 ____ 4 ____ 4 ____ ns tWHZ(1) Write Enab le to Output in High-Z 0 6060 10 0 11 ns 2948 tbl 09 |
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