14.1

7

IDT71B74

BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM

COMMERCIAL TEMPERATURE RANGE

± 10%)

71B74S8

71B74S10

71B74S12

71B74S15

71B74S20

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Match Cycle

Address to MATCH Valid

—

8

—

10

—

12

—

15

—

20

ns

Chip Select to MATCH Valid

—

7

—

7

—

8

—

10

—

10

ns

(1)

Chip Select to MATCH HIGH

—

7

—

8

—

8

—

8

—

8

ns

Data Input to MATCH Valid

—

7

—

8

—

10

—

12

—

12

ns

(1)

OE LOW to MATCH HIGH

—

7

—

8

—

10

—

10

—

10

ns

(1)

WE LOW to MATCH HIGH

—

7

—

8

—

10

—

10

—

10

ns

(1)

RESET LOW to MATCH HIGH

—

8

—

10

—

10

—

12

—

15

ns

MATCH Valid Hold From Address

2

—

2

—

2

—

2

—

2

—

ns

MATCH Valid Hold From Data

2

—

2

—

2

—

2

—

2

—

ns

NOTE:

3013 tbl 12

1. This parameter is guaranteed with the AC Load (Figure 3) by device characterization, but is not production tested.

CS

CS Controlled Timing)

(1, 6)

NOTES:

1.

WE, CS must be inactive during all address transitions.

2. A write occurs during the overlap of a LOW

WE and a LOW CS.

CS or WE going HIGH to the end of the write cycle.

4. During this period, I/O pins are in the output state and input signals must not be applied.

5. If the

CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

6.

OE is HIGH during the WE controlled write cycle, this requirement does not

9. Transition is measured

±200mV from steady state.

3013 drw 12

CS

OE

ADDRESS

WE

DATA VALID

(5)

(7)

(2)