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IDT49FCT805CTQB Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT49FCT805CTQB Datasheet(HTML) 6 Page - Integrated Device Technology |
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6 / 7 page  IDT49FCT805BT/CT, 806BT/CT FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES 9.2 6 TEST CIRCUITS AND WAVEFORMS TEST CIRCUIT FOR ALL OUTPUTS ENABLE AND DISABLE TIME SWITCH POSITION Test Switch Disable LOW Enable LOW Closed Disable HIGH Enable HIGH Open DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 2920 lnk 08 Pulse Generator R T D.U.T. VCC VIN C L V OUT 50pF 500 Ω 500 Ω 7.0V 2920 drw 07 tPLH1 OUTPUT 1 OUTPUT 2 tSK(o) tPLH2 3V 0V VOH 1.5V 1.5V VOL VOH 1.5V VOL INPUT tPHL1 tPHL2 tSK(o) tSK(o) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1| CONTROL INPUT OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH 3V 1.5V 0V 3.5V 0V SWITCH CLOSED SWITCH OPEN V OL VOH 0.3V 0.3V t PLZ t PZL t PZH t PHZ 3.5V 0V 1.5V 1.5V ENABLE DISABLE 3V 0V VOH tPLH tPHL VOL 1.5V 1.5V tR tF 2.0V 0.8V INPUT OUTPUT INPUT tPLH1 PACKAGE 1 OUTPUT PACKAGE 2 OUTPUT tSK(t) tPLH2 3V 0V VOH 1.5V 1.5V VOL VOH 1.5V VOL tPHL1 tPHL2 tSK(t) tSK(t) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1| tPLH tPHL 3V 0V VOH 1.5V 1.5V VOL tSK(p) = |tPHL - tPLH| INPUT OUTPUT PULSE SKEW - tSK(p) PACKAGE SKEW - tSK(t) PACKAGE DELAY OUTPUT SKEW- tSK(o) Package 1 and Package 2 are same device type and speed grade ENABLE AND DISABLE TIMES 2920 drw 08 2920 drw 10 2920 drw 09 2920 drw 11 2920 drw 12 NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: f ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns |
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