6.3

7

IDT6198S/L

CMOS STATIC RAM 64K (16K x 4-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (

WE

WE CONTROLLED TIMING)

(1, 2, 3, 7)

CS

ADDRESS

WE

OE

2987 drw 10

(4)

(6)

(4)

(6)

DATA VALID

NOTES:

1.

WE or CS must be HIGH during all address transitions.

CS and a LOW WE.

CS or WE going HIGH to the end of the write cycle.

4. During this period, I/O pins are in the output state so that the input signals must not be applied.

5. If the

CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

6. Transition is measured

±200mV from steady state.

7. If

OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (

CS

CS CONTROLLED TIMING)

(1, 2, 3)

CS

ADDRESS

WE

2987 drw 11

DATA VALID