5.35

7

COMMERCIAL TEMPERATURE RANGE

IDT72105, IDT72115, IDT72125,

256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO

2665 drw 09

SOCP

W

EF

0

1

n–1

SO

NOTE 1

NOTE 2

2665 drw 11

SOCP

W

HF

AEF

AEF

HALF-FULL (1/2)

HALF-FULL

7/8 FULL

7/8 FULL

ALMOST-EMPTY

(1/8 FULL – 1)

ALMOST-EMPTY

(1/8 FULL – 1)

ALMOST-FULL (7/8 FULL + 1)

1/8 FULL

HALF-FULL + 1

Figure 8. Half-Full, Almost-Full and Almost-Empty Timings

NOTE:

1.

Single Device Mode will not tri-state but will retain the last valid data.

Figure 7. Full Boundary Condition Timing

2665 drw 10

SOCP

W

FF

0

SO

1

n–1

NOTE 1

NOTE 1

NOTE:

1.

Once

EF has gone LOW and the last bit of the final word has been shifted out, SOCP should not be clocked until EF goes HIGH.

2.

In Single Device Mode, SO will not tri-state except after Reset. It will retain the last valid data.

Figure 6. Empty Boundary Condition Timing