5.35

5

COMMERCIAL TEMPERATURE RANGE

IDT72105, IDT72115, IDT72125,

256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO

AC TEST CONDITIONS

2665 tbl 07

NOTES:

1.

2.

SOCP should be in the steady LOW or HIGH during tRSS. The first LOW-HIGH (or HIGH-LOW) transition can begin after tRSR.

Figure 1. Reset

FUNCTIONAL DESCRIPTION

Parallel Data Input

The device must be reset before beginning operation so

that all flags are set to their initial state. In width or depth

expansion the First Load pin (

FL) must be programmed to

indicate the first device.

15

input data lines. A write cycle is initiated on the falling edge

of the Write (

W) signal provided the Full Flag (FF) is not

asserted. If the

W signal changes from HIGH-to-LOW and the

Full Flag (

FF) is already set, the write line is internally inhibited

internally from incrementing the write pointer and no write

operation occurs.

Data set-up and hold times must be met with respect to the

rising edge of Write. On the rising edge of

W, the write pointer

is incremented. Write operations can occur simultaneously or

asynchronously with read operations.

Serial Data Output

The serial data is output on the SO pin. The data is clocked

out on the rising edge of SOCP providing the Empty Flag (

EF)

is not asserted. If the Empty Flag is asserted then the next data

word is inhibited from moving to the output register and being

clocked out by SOCP.

The serial word is shifted out Least Significant Bit or Most

Significant Bit first, depending on the

FL/DIR level during

operation. A LOW on DIR will cause the Least Significant Bit

to be read out first. A HIGH on DIR will cause the Most

Significant Bit to be read out first.

°C, f = 1.0MHz)

Symbol

Conditions

Max.

Unit

Input Capacitance

10

pF

Output

Capacitance

12

pF

NOTE:

2665 tbl 08

1. This parameter is sampled and not 100% tested.

W

RS

AEF, EF

HF, FF

FLAG

STABLE

FLAG

STABLE

2665 drw 04

SOCP

NOTE 2

FL/DIR

Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

5ns

Input Timing Reference Levels

1.5V

Output Reference Levels

1.5V

Output Load

See Figure A

or equivalent circuit

Figure A. Output Load

*Includes jig and scope capacitances.

2665 drw 03

1.1K

Ω

30pF

680

Ω

5V

TO

OUTPUT

PIN

*